A method of allocating variables to computer memory includes determining at compile time when each of the plurality of variables is live in a memory region and allocating a memory region to each variable wherein at least some variables are allocated at compile time to overlapping memory regions to be stored in those memory regions at runtime at non-overlapping times.

A method for generating and updating a live dashboard of a building management system for a building includes generating a dashboard designer interface and causing the dashboard designer interface to be displayed on a user device of a user, receiving a graphic element from the user, wherein the graphic file supports animation and user interaction, generating a widget by binding the graphic element received from the user to a widget of the live dashboard, binding a data point to the widget based on a user selection via the dashboard designer interface, wherein the data point being a data point of building equipment of the building, receiving a value for the data point from the building equipment, and displaying the widget in the live dashboard, the widget including an indication of the value for the data point.

In a system for automatic generation of event-driven, tuple-space based programs from a sequential specification, a hierarchical mapping solution can target different runtimes relying on event-driven tasks (EDTs). The solution uses loop types to encode short, transitive relations among EDTs that can be evaluated efficiently at runtime. Specifically, permutable loops translate immediately into conservative point-to-point synchronizations of distance one. A runtime-agnostic which can be used to target the transformed code to different runtimes.

An example embodiment may involve obtaining one or more blueprint files. The blueprint files may collectively define a system of processing nodes, a call flow involving a sequence of messages exchanged by the processing nodes, and message formats of the messages exchanged by the processing nodes. The example embodiment may also involve compiling the blueprint files into machine executable code. The machine executable code may be capable of: representing the processing nodes as decomposed, dynamically invoked units of logic, and transmitting the sequence of messages between the units of logic in accordance with the message formats. The units of logic may include a respective controller and one or more respective workers for each type of processing node.

An information processing method executed by a computer, the method includes executing a target program to acquire number of executions for each of a plurality of program codes; selecting a combination of program codes related to a plurality of assignment statements from among program codes related to assignment statements having a higher number of executions based on the acquired number of executions; when the target program is changed, executing the changed target program to calculate an execution accuracy and an operation time so that parallel processing using an SIMD operation function is executed for each of the program codes related to the plurality of assignment statements included in the selected combination; and searching for the combination so that the calculated execution accuracy and operation time satisfy a predetermined condition.

Computer processing and outcome prediction systems and methods used to generate algorithm time prediction polynomials, inverse algorithm time prediction polynomials, determine race conditions, determine when a non-linear algorithm can be treated as if it were linear, as well as automatically generate parallel and quantum solutions from classical software or from the relationship between monotonic attribute values.

Various arrangements for facilitating smart television content receivers are provided. A primary television receiver (PTR) having a first operating system may be configured to receive digital content from a remote content provider and distribute the content to one or more devices in response to a request for the content. A secondary television receiver (STR) configured to be in communication with a PTR and having a second operating system may be configured to receive the digital content from the PTR and provide the content to a display for presentation. The STR may include a first software stack including a first inter-process communication (IPC) mechanism, and a second software stack including the first IPC mechanism and a second IPC mechanism. The first IPC may support communication within the first stack as well as between the first stack and the second stack. The second IPC may support communication within the second stack.

A method comprises a compiler determining operators and matrices of an application model. The compiler generates a dimension-based search space (DBSS) comprising Named Nodes corresponding to the operators. The Named Nodes comprise a Named DIM corresponding to a matrix associated with an operator. The Named DIM comprises a DIM Name corresponding to a dimension of a row or column of the matrix. The DBSS comprises an application programming interface (API) to determine operators, matrices, and/or attributes of operators/matrices of the application model using the DIM Names. The method includes the compiler determining the operator, the matrix, and the Named DIM and generating an entry in the DBSS that includes a Named Node corresponding to the operator, a Named DIM corresponding to the matrix and including the DIM Name. A computing system and/or a computer program product can implement the method.

Automatic workflow generation is described. One or more files containing code statements for accessing and modifying information in a destination database is received. The code statements are parsed from the one or more files and dependencies between the code statements are determined. A dependency graph is built by arranging the code statements according to the dependencies between the code statements. The dependency graph is partitioned by identifying at least one barrier code statement having an unclear dependency and dividing the dependency graph between code statements occurring prior to the at least one barrier code statement and code statements occurring after the at least one barrier code statement. Jobs are scheduled based on the partitioned dependency graph, and the code statements are annotated according to the scheduled jobs. A workflow is then automatically generated based on the annotated code statements.

The technology disclosed relates to allocating available physical compute units (PCUs) and/or physical memory units (PMUs) of a reconfigurable data processor to operation units of an operation unit graph for execution thereof. In particular, it relates to selecting, for evaluation, an intermediate stage compute processing time between lower and upper search bounds of a generic stage compute processing time, determining a pipeline number of the PCUs and/or the PMUs required to process the operation unit graph, and iteratively, initializing new lower and upper search bounds of the generic stage compute processing time and selecting, for evaluation in a next iteration, a new intermediate stage compute processing time taking into account whether the pipeline number of the PCUs and/or the PMUs produced for a prior intermediate stage compute processing time in a previous iteration is lower or higher than the available PCUs and/or PMUs.