Patent classifications
G06F9/223
Configure a Coarse Grained Reconfigurable Array to Execute Instructions of a Program of Data Flows
Control a coarse grained reconfigurable array during execution of an assembly language program identifying data flows through memory locations represented by memory variables. For example, a lowering program can be configured to receive the assembly language program, a hardware profile of the coarse grained reconfigurable array, and an instruction execution schedule to generate a configuration usable to control the coarse grained reconfigurable array. The lowering program can identify tile memories used to implement the memory locations represented by the memory variables in the assembly language program, and trace the data flows specified in the assembly language program. Using timing of instruction execution identified in the schedule, the lowering program can determine timing and controls for the dispatch interface, memory interfaces, and internal connections within tiles of the coarse grained reconfigurable array during execution of the assembly language program.
Systems and methods for processing Software Application notifications
Methods and systems for managing notifications relating to execution of microservices are described herein. A format of notifications relating to execution of a plurality of microservices may be defined. The format may provide that all notifications generated based on the format comprise code. The code may indicate, for example, an identity of one of a plurality of microservices, a version of the code, an occurrence of an issue in execution of the one of the plurality of microservices, and/or one or more scripts which may be executed to address an issue of the notification. Two or more notifications may be received, and the one or more notifications may be formatted based on the defined format. A third notification may be generated based on a comparison of the two or more notifications. The third notification may be transmitted to a computing device.
Systems and methods for distributed business process management
Systems and methods for distributed business process management are disclosed. In one embodiment, in an information processing apparatus comprising at least one computer processor, a method for configuration-driven distributed orchestration using different software components to execute a complex business process may include: (1) receiving a request for a runtime flow from a flow management adapter; (2) reading a flow configuration from the request; (3) creating an instance of the runtime flow; (4) initiating a service call to each component in the runtime flow; (5) creating a runtime instance in a database along with a state of each dependency in the runtime flow; and in response to external dependencies being met: (6) building and sending message to the components using a message builder; (7) initiating flow actions via an event-driven scheduler; and (8) making a service call to at least one of the components using the message builders.
Microprocessor with pipeline control for executing of instruction at a preset future time
In the disclosure, the microprocessor resolves the conflicts in decode stage and schedules the instruction to be executed at a future time. The instruction is issued to an execution queue until the scheduled time in the future when it is dispatched to a functional unit for execution. The disclosure uses a counter for the functional unit to track when the resource is available in the future to accept the next instruction. The disclosure also tracks the future N cycles when the register file read and write ports are scheduled to read and write operand data.
SYNCHRONOUS MICROTHREADING
Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
SYNCHRONOUS MICROTHREADING
Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
SYNCHRONOUS MICROTHREADING
Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
Apparatus and method for specifying quantum operation parallelism for a quantum control processor
Apparatus and method for specifying quantum operation parallelism. For example, one embodiment of an apparatus comprises: instruction fetch circuitry to fetch a plurality of quantum instructions from a memory or a cache; slice-based instruction processing circuitry to identify quantum circuit slices comprising sets of one or more of the plurality of quantum instructions; and one or more instruction decoders to decode the quantum instructions to generate quantum microoperations; and quantum execution circuitry to execute sets of the quantum microoperations in parallel based on the quantum circuit slices.
Neural network calculation apparatus and method
The present disclosure discloses a neural network processing module, in which a mapping unit is configured to receive an input neuron and a weight, and then process the input neuron and/or the weight to obtain a processed input neuron and a processed weight; and an operation unit is configured to perform an artificial neural network operation on the processed input neuron and the processed weight. Examples of the present disclosure may reduce additional overhead of the device, reduce the amount of access, and improve efficiency of the neural network operation.
3-level real-time concurrent production operation workgroup systems for fine-grained proactive closed loop problem solving operations
A method of utilizing 3-level wHCSs created in the first generation to accommodate 3-level conveyer-integrated workgroups in a production facility to make these workgroups work collaboratively as one Task crew-entity is disclosed. By installing the 3-level 3-link-typed TeamProcessors in a 3-level wHCS with Task feedback-control operation-oriented OSs, Task operation programs and Task-operation and management libraries, a 3-level Task operation workgroup-computing Entity-oriented system, can be established to support the Task crew-entity as a whole and provide fine-grained-proactive closed-loop-problem-solving (PS) operations for external users, collaborators and supervisors in a real-time concurrent and secure manner, abiding by the self-improving solution-domain PS-principle.