G06F9/226

Vector cumulative sum instruction and circuit for implementing filtering operations
11829756 · 2023-11-28 · ·

A vector cumulative sum circuit can include a set of input registers, a carry-forward data source, a set of output registers, and a network of adder circuits coupling the input registers to the output registers such that the output value in a given output register is the sum of a value provided by the carry-forward data source and the input values from all of the input registers (in logical order) up to (and including) the corresponding input register. The value in the last output register can be carried forward to enable cumulative summing of a larger number of input values. The vector cumulative sum circuit can be implemented in a programmable processor, and a vector cumulative sum instruction can be defined in the instruction set. Using the vector cumulative sum circuit and instruction, filtering operations can be accelerated.

Splitting vector instructions into microinstructions for parallel execution based on index comparisons of completed microinstructions

This disclosure provides an instruction transmitting unit, an instruction execution unit, and a related apparatus and method. The instruction transmitting unit includes: an instruction splitter adapted to split a to-be-executed vector instruction into microinstructions; a microinstruction index fetcher adapted to acquire a number-of-effective-elements index of the microinstructions resulting from the splitting based on an element range involved in the microinstructions; an index comparison subunit adapted to compare the acquired number-of-effective-elements index with a first index, where the first index is a number-of-effective-elements index of a fault-only-first microinstruction whose processing has not been completed; and a microinstruction transmission controller adapted to transmit the microinstructions resulting from the splitting to a vector execution unit for execution when the number-of-effective-elements index is less than the first index. This disclosure improves operating efficiency of subsequent vector instructions when a fault-only-first vector loading instruction is involved in chaining.

Electronic apparatus, system and method capable of remotely maintaining the operation of electronic apparatus
11385971 · 2022-07-12 · ·

The invention provides a system capable of remotely maintaining the operation of electronic apparatus. The system comprises a cloud management platform and at least one electronic apparatus. The electronic apparatus comprises a data storage device and an operating system maintenance device. The data storage device comprises a plurality of flash memories and a controller. The operating system maintenance device comprises a microprocessor and a network communication component. An operating system is installed in the flash memories of the data storage device. When the operating system of the electronic device is abnormal, the operating system maintenance device receives an operating system repairing instruction from the cloud management platform via the network communication component. The microprocessor of the cloud management platform repairs the operating system of the electronic apparatus according to the operating system repairing instruction, so that the operating system of the electronic apparatus can resume normal operation.

Microservice decomposition strategy of monolithic applications

Systems and techniques that facilitate automated recommendation of microservice decomposition strategies for monolithic applications are provided. In various embodiments, a community detection component can detect a disjoint code cluster in a monolithic application based on a code property graph characterizing the monolithic application. In various aspects, the code property graph can be based on a temporal code evolution of the monolithic application. In various embodiments, a topic modeling component can identify a functional purpose of the disjoint code cluster based on a business document corpus corresponding to the monolithic application. In various embodiments, a microservices component can recommend a microservice to replace the disjoint code cluster based on the functional purpose.

MICRO-APPLICATION CREATION AND EXECUTION
20220261244 · 2022-08-18 · ·

A method for creating and executing a micro-application includes receiving a user selection of a user interface element within a user interface of a primary application. Source code associated with the selected user interface element is parsed to obtain at least one attribute associated with the selected user interface element. Data associated with the selected user interface element is identified based on the source code. A response based on the at least one attribute and the data is generated. A microapp configured to process the response to obtain the data from within the primary application is generated.

Instruction execution method and instruction execution device

An instruction execution method includes the following steps: translating a macro-instruction into a first micro-instruction and a second micro-instruction, and marking first binding information on the first micro-instruction, and marking second binding information on the second micro-instruction; and simultaneously retiring the first micro-instruction and the second micro-instruction according to the first binding information and the second binding information. The first micro-instruction and the second micro-instruction are adjacent to one another in the micro-instruction storage space.

VIRTUAL MACHINE FOR VIRTUALIZING GRAPHICS FUNCTIONS

A host computer for emulating a target system includes a host memory, a CPU, and a host GPU. The host memory is configured to store a library of graphics functions and a VM. The VM includes a section of emulated memory storing target code configured to execute on the target system. The CPU is configured to execute the VM to emulate the target system. The VM is configured to execute the target code and intercept a graphics function call in the target code. The VM is further configured to redirect the graphics function call to a corresponding graphics function in the library of graphics functions stored in the host memory. The host GPU is configured to execute the corresponding graphics function to determine at least one feature configured to be rendered on a display coupled to the host GPU.

Automatically mapping data while designing process flows

An example method facilitates associating data objects with elements of a process to be implemented via a process-based software application. The example method includes determining that a developer has added a particular software element to a software application being developed by the developer; accessing metadata describing the software element; and using the metadata to automatically associate the software element to one or more data objects to be used by the software element during running of the software application. A process cloud may facilitate implementing the method by automatically performing data mapping for software elements, such as approval tasks, forms, and so on, by determining appropriate task outcome data objects with reference to data characterizing a software flow of the software application, and by similarly automatically selecting and/or creating data objects for forms, which may be associated with or used by a task.

Apparatus and methods for debugging on a host and memory device
11074988 · 2021-07-27 · ·

Apparatus and methods for debugging on a host and memory device include an example apparatus comprising a memory device having an array of memory cells. Sensing circuitry is coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry, the controller is configured to control performance of the logical operations. An interface is configured to receive a debugging indication and to cause the controller to halt a logical operation on the memory device.

Adjusting thread balancing in response to disruptive complex instruction

A computer-implemented method is provided and includes allocating, by a processor, an instruction to a first thread, decoding, by the processor, the instruction, determining, by the processor, a type of the instruction based on information obtained by decoding the instruction, and based on determining that the instruction is a disruptive complex instruction, changing a mode of allocating hardware resources to an instruction-based allocation mode. In the instruction-based allocation mode, the processor adjusts allocation of the hardware resources among a first thread and a second thread based on types of instructions allocated to the first and second threads.