A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

Hardware processors and methods for extended microcode patching through on-die and off-die secure storage are described. In one embodiment, the additional storage resources used for storing micro-operations are section(s) of a cache that are unused at runtime and/or unused by a configuration of a processor. For example, the additional storage resources may be a section of a cache that is used to store context information from a core when the core is transitioned to a power state that shuts off voltage to the core. Non-limiting examples of such sections are one or more sections for storage of context information for a transition of a thread to idle or off, storage of context information for a transition of a core for a multiple core processor to idle or off, or storage of coherency information for a transition of a cache coherency circuit (e.g., cache box (CBo)) to idle or off.

Hardware processors and methods for extended microcode patching through on-die and off-die secure storage are described. In one embodiment, the additional storage resources used for storing micro-operations are section(s) of a cache that are unused at runtime and/or unused by a configuration of a processor. For example, the additional storage resources may be a section of a cache that is used to store context information from a core when the core is transitioned to a power state that shuts off voltage to the core. Non-limiting examples of such sections are one or more sections for storage of context information for a transition of a thread to idle or off, storage of context information for a transition of a core for a multiple core processor to idle or off, or storage of coherency information for a transition of a cache coherency circuit (e.g., cache box (CBo)) to idle or off.

A method of initializing an application-specific integrated circuit (ASIC), the method including reading, by a boot microcode engine integrated with the ASIC, microcode from an electrically programmable non-volatile memory (EP-NVM) integrated on a same die as the ASIC. The method further includes writing the microcode onto internal memories of a micro-controller of the ASIC and initializing the micro-controller by the boot microcode engine. The method also includes loading, by the micro-controller, a full boot image from an additional storage device distinct from the EP-NVM onto the internal memories of the micro-controller and initializing the ASIC by the micro-controller based on the full boot image.

A method of initializing an application-specific integrated circuit (ASIC), the method including reading, by a boot microcode engine integrated with the ASIC, microcode from an electrically programmable non-volatile memory (EP-NVM) integrated on a same die as the ASIC. The method further includes writing the microcode onto internal memories of a micro-controller of the ASIC and initializing the micro-controller by the boot microcode engine. The method also includes loading, by the micro-controller, a full boot image from an additional storage device distinct from the EP-NVM onto the internal memories of the micro-controller and initializing the ASIC by the micro-controller based on the full boot image.

Systems and methods are disclosed for derivation of executable tasks for synchronizing configuration parameters. An example method may comprise: obtaining a first set of configuration parameters of a first computer system corresponding to a first time value; obtaining a second set of configuration parameters of the first computer system corresponding to a second time value; performing a comparison between the first set of configuration parameters and the second set of configuration parameters to determine one or more differences; deriving in view of the comparison, one or more executable tasks to convert the first set of configuration parameters to the second set of configuration parameters; and providing, to a second computer system, the one or more executable tasks for execution by the second computer system to synchronize configuration parameters of the second computer system to configuration parameters of the first computer system corresponding to the second time value.

In one implementation, systems and methods are provided for developing a computer-implemented digital experience application having a first and a second micro-application. Each micro-application includes a front end interface configured to receive and display information. The first micro-application includes a first event manager configured to detect an application event belonging to a category, and a first state manager configured to detect an application state belonging to the category. The digital experience application further includes a driver application configured to host the first and second micro-applications, an event hub configured to receive the detected application event from the first micro-application, and a state store configured to store the detected application state received from the first micro-application. The second micro-application includes a second event manager configured to receive the detected application event from the event hub, and a second state manager configured to receive the detected application state from the state store.

Embodiments disclosed are directed to a system that performs steps to transmit, to a client device, a host application for storage on a browser of the client device. The host application is used to facilitate loading of a micro-frontend application onto the browser at runtime of the host application, for integration with and use in conjunction with the host application. The system also receives, from the host application, a request to load the micro-frontend application onto the browser. Based on receiving the request, a manifest file is accessed indicating a version of the micro-frontend application to be loaded onto the browser. The micro-frontend application is retrieved based on the version indicated in the manifest file and transmitted to the host application for loading onto the browser.

Embodiments disclosed are directed to a system that performs steps to transmit, to a client device, a host application for storage on a browser of the client device. The host application is used to facilitate loading of a micro-frontend application onto the browser at runtime of the host application, for integration with and use in conjunction with the host application. The system also receives, from the host application, a request to load the micro-frontend application onto the browser. Based on receiving the request, a manifest file is accessed indicating a version of the micro-frontend application to be loaded onto the browser. The micro-frontend application is retrieved based on the version indicated in the manifest file and transmitted to the host application for loading onto the browser.

This disclosure provides an instruction transmitting unit, an instruction execution unit, and a related apparatus and method. The instruction transmitting unit includes: an instruction splitter adapted to split a to-be-executed vector instruction into microinstructions; a microinstruction index fetcher adapted to acquire a number-of-effective-elements index of the microinstructions resulting from the splitting based on an element range involved in the microinstructions; an index comparison subunit adapted to compare the acquired number-of-effective-elements index with a first index, where the first index is a number-of-effective-elements index of a fault-only-first microinstruction whose processing has not been completed; and a microinstruction transmission controller adapted to transmit the microinstructions resulting from the splitting to a vector execution unit for execution when the number-of-effective-elements index is less than the first index. This disclosure improves operating efficiency of subsequent vector instructions when a fault-only-first vector loading instruction is involved in chaining.