Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.

A method for executing a program by a computer system executing sequences of instructions, includes a conditional selection of a sequence of instructions from a satisfied sequence and at least one unsatisfied sequence. The method comprising includes on the execution of a sequence distribution instruction by a first calculation resource, distributing the execution of the satisfied sequence and the at least one unsatisfied sequence between the first calculation resource and at least one second calculation resource. The method also includes parallel execution of the satisfied sequence and of the at least one unsatisfied sequence each by a calculation resource among the first and the at least one second calculation resource. The method further includes, once the satisfied sequence and the at least one unsatisfied sequence are fully executed, continuing the execution of program by a calculation resource among the first and the at least one second calculation resource.

Technologies for providing streamlined provisioning of accelerated functions in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to determine whether to accelerate a function of a workload executed by the compute sled, and send, to a memory sled and in response to a determination to accelerate the function, a data set on which the function is to operate. The circuitry is also to receive, from the memory sled, a service identifier indicative of a memory location independent handle for data associated with the function, send, to a compute device, a request to schedule acceleration of the function on the data set, receive a notification of completion of the acceleration of the function, and obtain, in response to receipt of the notification and using the service identifier, a resultant data set from the memory sled. The resultant data set was produced by an accelerator device during acceleration of the function on the data set. Other embodiments are also described and claimed.

Technologies for providing streamlined provisioning of accelerated functions in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to determine whether to accelerate a function of a workload executed by the compute sled, and send, to a memory sled and in response to a determination to accelerate the function, a data set on which the function is to operate. The circuitry is also to receive, from the memory sled, a service identifier indicative of a memory location independent handle for data associated with the function, send, to a compute device, a request to schedule acceleration of the function on the data set, receive a notification of completion of the acceleration of the function, and obtain, in response to receipt of the notification and using the service identifier, a resultant data set from the memory sled. The resultant data set was produced by an accelerator device during acceleration of the function on the data set. Other embodiments are also described and claimed.

In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

A method comprises receiving at a compiler a bit file description and a program, said bit file description comprising a description of routing of a part of a circuit. The method comprises compiling the program using said bit file description to output a bit file for said program.

A method comprises receiving at a compiler a bit file description and a program, said bit file description comprising a description of routing of a part of a circuit. The method comprises compiling the program using said bit file description to output a bit file for said program.