Systems, apparatuses, and methods related to an extended memory neuromorphic component for performing operations in memory are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit and a memory array. The example apparatus can further include a communication subsystem coupled to the at least one of the plurality of computing devices and to a neuromorphic component. At least one of the plurality of computing devices can receive a request from a host to perform an operation, receive an indication of data to be access in a memory device to perform the operation, and send an indication to the neuromorphic component to monitor the data to be accessed. The neuromorphic component can intercept data and determine that a portion of the data should be flagged.

The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread architecture, the general-purpose graphics compute unit to concurrently execute the first instruction and the second instruction.

An apparatus comprising at least one interface configured to read one or more high-level code instructions; and at least one processor configured to read the one or more high-level code instructions using the interface, determine atomic operations in the high-level code instructions, and translate the one or more high-level code instructions into assembly code instructions, wherein atomic operations are indicated in the assembly code instructions based on the atomic operations in the high-level code instruction.

Processing circuitry performs processing operations specified by program instructions. An instruction decoder decodes an atomic-add-with-carry instruction AAD-DC to control the processing circuitry to perform an atomic operation of an add of an addend operand value and a data value stored in a memory to generate a result value stored in the memory and a carry value indicative of whether or not the add generated a carry out.

A microprocessor for a vehicle control device includes: an instruction set; a register section with a status register, a first flag being provided in the status register for storing a logical result of a comparison operation; and an arithmetic logical unit. The status register comprises a second flag for storing the logical result of a second comparison operation. The instruction set comprises a first additional instruction, which performs a comparison among two handed-over operands, a result of the comparison being stored in the second flag. The instruction set comprises a second additional instruction, which selects and performs one of at least three pre-defined operations on a basis of a logic connection of values in the first flag and the second flag, for updating an upper boundary and/or a lower boundary of a search field in a binary search for a next iteration.

An apparatus includes a buffer, a sequencing circuit, and an execution unit. The buffer may be configured to store a plurality of instructions. Each of the plurality of instructions may be in a first thread. In response to determining that the first instruction depends on the value of a condition variable and to determining that a count value is below a predetermined threshold, the sequencing circuit may be configured to add a wait instruction before the first instruction. The execution unit may be configured to delay execution of the first instruction for an amount of time after executing the wait instruction. The sequencing circuit may be further configured to maintain the plurality of instructions in the first buffer after executing the wait instruction, and to decrement the count value in response to determining that the value of the condition variable is updated within the amount of time.

In one embodiment, a processor includes an instruction decoder to receive a first instruction having a prefix and an opcode and to generate, by an instruction decoder of the processor, a second instruction executable based on a condition determined based on the prefix, and an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix.

A hardware execution unit within a processor core executes a second instruction, which is part of a software thread, and which is executed out of order within the software thread. A sticky bit flip detection hardware device detects a change to a sticky bit in a floating-point status and control register (FPSCR) within the processor core. An instruction issue hardware unit identifies a first instruction that is in the software thread that is capable of reading or clearing the sticky bit. A flushing execution unit flushes all results of instructions from an instruction completion table (ICT) that include and are after the first instruction in the software thread. A hardware dispatch device dispatches all instructions that include and are after the first instruction in the software thread for execution by one or more hardware execution units within the processor core in a next-to-complete (NTC) sequential order.

An instruction to perform a comparison of a first value and a second value is executed. Based on a control of the instruction, a compare function to be performed is determined. The compare function is one of a plurality of compare functions configured for the instruction, and the compare function has a plurality of options for comparison. A compare option based on the first value and the second value is selected from the plurality of options defined for the compare function, and used to compare the first value and the second value. A result of the comparison is then placed in a select location, the result to be used in processing within a computing environment.