Alternative reporting channels are implemented for interrupts to a microcontroller device. An access device for a microcontroller may support performing requests from a microcontroller to controlled devices via an interconnect. The access device may have a separate communication channel with at least one of the controlled devices to receive interrupts. When an interrupt is signaled, an indication of the interrupt may be stored at a storage device at the access device. The microcontroller may read from the storage device at the access device to obtain the indication of the interrupt.

Described herein is a computer implemented method. The method comprises executing an application defining a feature flag, the execution of the application being associated with a user identifier. The method further comprises determining if version data associated with the feature flag and user identifier is stored in a local data store. In response determining that the version data associated with the feature flag and user identifier is stored in the local data store an evaluation request is generated that includes the version data and the user identifier. The evaluation request is then communicated to a feature flag evaluation service.

Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. For example, traversal efficiency is improved by combining programmable traversals based on ray operations with per-node static configurations that modify traversal behavior. The per-node static configurations enable creators of acceleration data structures to optimize for potential traversals without necessarily requiring detailed information about ray characteristics and ray operations used when traversing the acceleration structure. Moreover, by providing for selective exclusion of certain nodes using per-node static configurations, less memory is needed to express an acceleration structure that includes, for example, different geometric levels of details corresponding to a single object.

A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Described is an apparatus comprising a first circuitry and a second circuitry. The first circuitry may process a sequence of Graphics Processing Unit (GPU) commands including an instruction carrying a flag that indicates a workload characteristic corresponding with the sequence of GPU commands. The second circuitry may initiate a power-directed parameter adjustment based upon the flag.

The present invention discloses an instruction processing apparatus, comprising a first register adapted to store first source data, a second register adapted to store second source data, a third register adapted to store accumulated data, a decoder adapted to receive and decode a multiply-accumulate instruction, and an execution unit. The multiply-accumulate instruction indicates that the first register serves as a first operand, the second register serves as a second operand, the third register serves as a third operand, and a shift flag. The execution unit is coupled to the first register, the second register, the third register, and the decoder, and configured to execute the decoded multiply-accumulate instruction so as to acquire the first source data from the first register and acquire the second source data from the second register, perform a multiplication operation on the first source data and the second source data so as to obtain a multiplication result, shift the multiplication result according to the shift flag, and add the shifted multiplication result and the accumulated data in the third register so as to obtain a multiply-accumulate result. The present invention further discloses a corresponding instruction processing method, a computing system, and a system on chip.

A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

An apparatus comprises: an instruction decoder to decode instructions; processing circuitry to perform data processing in response to the instructions decoded by the instruction decoder; and memory attribute checking circuitry to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a plurality of memory attribute entries, each memory attribute entry specifying access permissions for a corresponding address region of variable size within an address space. In response to a range checking instruction specifying address identifying parameters for identifying a first address and a second address, the instruction decoder controls the processing circuitry 4 to set, in at least one software-accessible storage location; a status value indicative of whether the first address and the second address correspond to the same memory attribute entry.

A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Vector add-with-carry instructions are described which use some elements of a destination vector register, or corresponding fields of a predicate register, to provide the carry information corresponding to results of an add-with-carry operation. This is useful for accelerating computations involving multiplications of long integer values.