A memory circuit included in a computer system includes a memory array that stores multiple program instructions included in compressed program code. In response to receiving a fetch instruction from a processor circuit, the memory circuit may retrieve a particular instruction from the memory array. The memory circuit may, in response to a determination that the particular instruction is a particular type of instruction, retrieve additional program instructions from the memory array using an address included in the particular instruction, and send the particular program instruction and the additional program instructions to the processor circuit.

A Multi-Purpose Dynamic Simulation and run-time Control platform includes a virtual process environment coupled to a physical process environment, where components/nodes of the virtual and physical process environments cooperate to dynamically perform run-time process control of an industrial process plant and/or simulations thereof. Virtual components may include virtual run-time nodes and/or simulated nodes. The MPDSC includes an I/O Switch which delivers I/O data between virtual and/or physical nodes, e.g., by using publish/subscribe mechanisms, thereby virtualizing physical I/O process data delivery. Nodes serviced by the I/O Switch may include respective component behavior modules that are unaware as to whether or not they are being utilized on a virtual or physical node. Simulations may be performed in real-time and even in conjunction with run-time operations of the plant, and/or simulations may be manipulated as desired (speed, values, administration, etc.). The platform simultaneously supports simulation and run-time operations and interactions/intersections therebetween.

Systems, devices, computer-implemented methods, and tangible non-transitory computer readable media for performing multilayered generation and processing of computer instructions are provided. For example, a computing device may receive a request with instructions in a first computer language, parse the instructions in the first computer language, analyze the instructions in the first computer language in view of information describing structure of a first application, generate instructions in a second computer language different from the first computer language where the instructions in the second computer language are generated based on the instructions in the first computer language and the information describing structure of the first application, obtain a result from a second application where the result comprises information based on the instructions in the second computing language, and provide the result in response to the request comprising the instructions in the first computer language.

Techniques are described for enabling a software modernization system to automatically map binary executable files and other runtime artifacts (e.g., application binaries, Java ARchive (JAR) files, .NET Dynamic Link Library (DLL) files, process identifiers, etc.) to source code associated with the binary executable files, e.g., as part of modernization processes aimed at migrating users' applications to a cloud service provider's infrastructure. A software modernization service of a cloud provider network provides discovery agents and other tools that are capable of creating an inventory of users' software applications and collecting profile data about the software applications. Various techniques are described for automatically identifying the source code associated with software applications identified by a discovery agent in a user's computing environment, thereby improving the efficiency of various software modernization analyses and other modernization processes.

A method for running an identity and access management system includes providing at least one layer, and a master computer that communicates with at least one slave computer. The master computer has at least one component which is designed as a computing device and/or as a memory device and/or as a further working component respectively. Units of the functionality of the computing device and/or of the memory device and/or of the further working component of the master computer, respectively, are generated. The respective units of the functionality of the computing device and/or of the memory device and/or of the functionality of the further working component, respectively, are converted into a code and are transmitted in coded form from the master computer to the slave computer. The master computer is controlled with the aid of the computing device and a software program.

Systems and methods for instruction decoding using hash tables. An example method of constructing a decoding tree comprises: generating an aggregated vector of differentiating bit scores representing at least a subset of a set of processor instructions; identifying, based on the aggregated vector of differentiating bit scores, one or more opcode bit positions; and constructing a hash table implementing a current level of a decoding tree representing the subset of the set of processor instructions, wherein the hash table is indexed by one or more opcode bits identified by the one or more opcode bit positions.

Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

In one example, an integrated circuit comprises: a memory configured to store a first mapping between a first opcode and first control information and a second mapping between the first opcode and second control information; a processing engine configured to perform processing operations based on the control information; and a controller configured to: at a first time, provide the first opcode to the memory to, based on the first mapping stored in the memory, fetch the first control information for the processing engine, to enable the processing engine to perform a first processing operation based on the first control information; and at a second time, provide the first opcode to the memory to, based on the second mapping stored in the memory, fetch the second control information for the processing engine, to enable the processing engine to perform a second processing operation based on the second control information.

Methods and apparatus relating to loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing are described. In an embodiment, Data-space Translation Logic (DTL) circuitry receives a static input and a dynamic input and generates one or more outputs based at least in part on the static input and the dynamic input. A frontend counter generates a count value for the dynamic input based at least in part on an incremented/decremented counter value and a next counter value from the DTL circuitry. The DTL circuitry is capable to receive a new dynamic input prior to consumption of the one or more outputs. Other embodiments are also disclosed and claimed.

Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.