Embodiments relate to event monitoring, identifying and predicting system comprises at least one database comprising an incoming data stream; a plurality of available data processing engines, each of the plurality of available data processing engines requiring an engine-specific event identifying instruction set; an abstraction engine configured to receive at least one engine-agnostic event identifying instruction set and convert the at least one engine-agnostic event identifying instruction set to an engine-specific event identifying instruction set suitable for a selected one of the plurality of available data processing engines; and a user interface comprising a data processing engine selector by which a user can provide the at least one engine-agnostic event identifying instruction set and select the one of the plurality of available data processing engines, and a report generator configured to provide an output result of processing at least a portion of the incoming data stream from the database by the selected one of the plurality of available data processing engines according to the engine-specific event identifying instruction set.

Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

A Multi-Purpose Dynamic Simulation and run-time Control platform includes a virtual process environment coupled to a physical process environment, where components/nodes of the virtual and physical process environments cooperate to dynamically perform run-time process control of an industrial process plant and/or simulations thereof. Virtual components may include virtual run-time nodes and/or simulated nodes. The MPDSC includes an I/O Switch which delivers I/O data between virtual and/or physical nodes, e.g., by using publish/subscribe mechanisms, thereby virtualizing physical I/O process data delivery. Nodes serviced by the I/O Switch may include respective component behavior modules that are unaware as to whether or not they are being utilized on a virtual or physical node. Simulations may be performed in real-time and even in conjunction with run-time operations of the plant, and/or simulations may be manipulated as desired (speed, values, administration, etc.). The platform simultaneously supports simulation and run-time operations and interactions/intersections therebetween.

Methods, systems, and computer program products for parameter management between programs with different addressing modes are described. A request may be received from a first program with a first addressing mode in a first runtime environment for calling a second program with a second addressing mode different from the first addressing mode, where at least one parameter included in the request is for calling the second program. A parameter area may be allocated in the first runtime environment for the at least one parameter. The at least one parameter may be stored in the allocated parameter area. The second program may be invoked based at least in part on the at least one parameter in the allocated parameter area. In this manner, parameter(s) may be communicated between the first program and the second program in an easy and effective way.

An apparatus and method for executing nested control flow instructions on a graphics processing unit (GPU). For example, one embodiment of a processor comprises: an execution unit having a plurality of channels to execute control flow instructions including fused control flow instructions comprising two or more consecutive control flow instructions fused into a single fused control flow instruction; and a branch unit to process the control flow instructions and to maintain a global counter indicating a nesting level of the control flow instructions, wherein to process a fused control flow instruction, the branch unit is to store a value N in a stack indicating a number of control flow instructions fused into the fused control flow instruction, the branch unit to subsequently read the value N from the stack upon execution of the fused control flow instruction and decrement the global counter by a value of N responsive to execution of the fused control flow instruction.

The technology disclosed herein pertains to a system and method for providing optimization of embedded computation instruction set (CIS), the method including downloading the CIS to a computational storage device (CSD), committing the CIS to a program slot in a computational storage processor of the CSD, simulating execution of the CIS at the committed slot to generate static analysis of one or more registers of the CIS to determine ranges of values that the one or more registers can take through a lifecycle of the CIS, demoting one or more of the registers to lower size registers, and generating a native instruction set from the CIS based on the register demotions.

According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly, checking for an Execution Unit (EXU) available for receiving a new instruction, and issuing the instruction to the available Execution Unit and entering a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).

The present application discloses a complex computing device, a complex computing method, an artificial intelligence chip and an electronic apparatus, and relates to a field of artificial intelligence chips. One of the solutions includes: an input interface receives complex computing instructions and arbitrates each complex computing instruction to a corresponding computing component respectively, according to the computing types in the respective complex computing instructions; each computing component is connected to the input interface, acquires a source operand from a complex computing instruction to perform complex computing, and generates computing result instruction to feed back to an output interface; the output interface arbitrates the computing result in each computing result instruction to the corresponding instruction source respectively, according to the instruction source identifier in each computing result instruction.

A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a field of a first instruction, a number of additional instructions to execute in conjunction with the first instruction and prior to execution of the first instruction.