A processing device is configured to process an initial set of command types. A command extension module and a digital signature are received. The digital signature is generated based on the command extension module using a private key of a key pair. The command extension module, once installed by the processing device, enables the processing device to process a new command type that is not included in the initial set of command types. The digital signature is verified using a public key of the key pair. Based on a successful verification of the digital signature, the command extension module is temporarily installed by loading the command extension module in a volatile memory device.

Instruction processing circuitry comprises fetch circuitry to fetch instructions for execution; instruction decoder circuitry to decode fetched instructions; execution circuitry to execute decoded instructions; and program flow prediction circuitry to predict a next instruction to be fetched; in which the instruction decoder circuitry is configured to decode a loop control instruction in respect of a given program loop and to derive information from the loop control instruction for use by the program flow prediction circuitry to predict program flow for one or more iterations of the given program loop.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obtaining a first schedule, for a first hardware block of an integrated circuit device, where the first schedule identifies a first set of operations to be performed by the first hardware block. Obtaining a second schedule for a second hardware block of the integrated circuit device, where the second schedule identifies a second set of operations to be performed by the second hardware block and where operations of the second schedule are coordinated with operations of the first schedule such that the first schedule triggers the first hardware block to send data to the second block at a first pre-scheduled value of a counter, and the second schedule triggers the second hardware block to accept the data at an input at a second pre-scheduled value of the counter that is after the first pre-scheduled value. Performing, by the first hardware block, the first set of operations according to the first schedule, and performing, by the second hardware block, the second set of operations according to the second schedule.

Facilitating per-CPU reference counting for multi-core systems with a long-lived reference is provided herein. A system includes a processor and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations. The operations include determining a first quantity of releases associated with an object in a data structure of the system and determining a second quantity of acquisitions associated with the object. The first quantity of releases can be distributed among respective first counters of processing elements of a group of processing elements. The second quantity of acquisitions can be distributed among respective second counters of the processing elements of the group of processing elements. Further, the operations can include, based on the second quantity of acquisitions and the first quantity of releases being determined to be a same value, implementing a removal of the object from the data structure.

In a digital communication system, a master device and a number of slave devices are coupled in communication with the master device over a shared data communication bus. During an address assignment procedure, the master device assigns different respective dynamic addresses to the slave devices in order to address the slave devices for data communication; during the address assignment procedure, the slave devices are arranged in a daisy-chain configuration, wherein each slave device has a daisy-chain input and a daisy-chain output, the daisy-chain input of a slave device being coupled to the daisy-chain output of a previous slave device in the daisy chain configuration, the daisy-chain input of a first slave device being coupled to a daisy-chain enabling output of the master device; in particular, the master device is configured to assign the respective dynamic addresses to the slave devices based on their arrangement in the daisy-chain configuration.

In one embodiment of the present invention, a programmable vision accelerator enables applications to collapse multi-dimensional loops into one dimensional loops. In general, configurable components included in the programmable vision accelerator work together to facilitate such loop collapsing. The configurable elements include multi-dimensional address generators, vector units, and load/store units. Each multi-dimensional address generator generates a different address pattern. Each address pattern represents an overall addressing sequence associated with an object accessed within the collapsed loop. The vector units and the load store units provide execution functionality typically associated with multi-dimensional loops based on the address pattern. Advantageously, collapsing multi-dimensional loops in a flexible manner dramatically reduces the overhead associated with implementing a wide range of computer vision algorithms. Consequently, the overall performance of many computer vision applications may be optimized.

An embodiment of the disclosed invention is a computer-implemented method for performing automated decision-making, which includes operating one or more loop(s) of sequential steps that receive data from the environment or from another source, interpret the data, decide on a course of action, and then execute the course of action. During the operation of the one or more loop(s), the method includes a self-monitor function that detects and corrects errors. Another embodiment is a loop architecture for performing automated decision-making that includes an API, three support modules, a receive module, an interpret module, a decide module, an execute module, and an orchestration layer. Another embodiment is a method for implementing a loop architecture to perform a task, wherein the method includes implementing handlers to perform the receive, interpret, decide, and execute functions, and implementing a topology definition.

Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a transaction pipeline and a pool of counters. The I/O agent circuit may initialize a first counter included in the pool of counters with an initial counter value. The I/O agent circuit may assign the first counter to a specific transaction type. The I/O agent circuit may increment the first counter as a part of allocating a transaction of a transaction type included in a set of transaction types different than the specific transaction type. Based on receiving a transaction request to process a first transaction of the specific transaction type, the I/O agent circuit may bind the first transaction to the first counter. The I/O agent circuit may issue the first transaction to the transaction pipeline based on a counter value stored by the first counter matching the initial counter value.

A serial peripheral interface (SPI) communication system includes a memory configured with a start register address and an end register address that define a register address range for a data operation; a chip select terminal configured to receive a chip select signal comprising an active and idle signal levels that define a plurality of chip select frames; a serial data input terminal configured to receive a master out, slave in (MOSI) signal, wherein the MOSI signal includes configuration information received in a first chip select frame of the data operation, wherein the configuration information includes an operation command bit indicating whether the data operation is a write operation or a read out operation and an auto-incrementation control bit indicating whether automatic register address incrementation across chip select frames is enabled or disabled; and a serial data output terminal configured to transmit a master in, slave out (MISO) signal.

A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.