Patent classifications
G06F9/448
Systems and method for flexible access of a regulated system
A method to provide flexible access to an internal data of an regulated system, the method comprising receiving, by a data access component of the regulated system, a loadable configuration file defining a set of triggering events and a set of memory, determining the occurrence of a single triggering event, accessing at least a subset of memory that contain the internal data of the avionics system to retrieve data associated with the one or more memory of the set of memory, and outputting the retrieved data to a receiving component.
Systems and method for flexible access of a regulated system
A method to provide flexible access to an internal data of an regulated system, the method comprising receiving, by a data access component of the regulated system, a loadable configuration file defining a set of triggering events and a set of memory, determining the occurrence of a single triggering event, accessing at least a subset of memory that contain the internal data of the avionics system to retrieve data associated with the one or more memory of the set of memory, and outputting the retrieved data to a receiving component.
MASKING ROW OR COLUMN POSITIONS FOR MATRIX PROCESSING
An apparatus comprises matrix processing circuitry to perform a matrix processing operation on first and second input operands to generate a result matrix, where the result matrix is a two-dimensional matrix; operand storage circuitry to store information for forming the first and second input operands for the matrix processing circuitry; and masking circuitry to perform a masking operation to mask at least part of the matrix processing operation or the information stored to the operand storage circuitry based on masking state data indicative of one or more masked row or column positions to be treated as representing a masking value. This is useful for improving performance of two-dimensional convolution operations, as the masking can be used to mask out selected rows or columns when performing the 2D convolution as a series of 1×1 convolution operations applied to different kernel positions.
MASKING ROW OR COLUMN POSITIONS FOR MATRIX PROCESSING
An apparatus comprises matrix processing circuitry to perform a matrix processing operation on first and second input operands to generate a result matrix, where the result matrix is a two-dimensional matrix; operand storage circuitry to store information for forming the first and second input operands for the matrix processing circuitry; and masking circuitry to perform a masking operation to mask at least part of the matrix processing operation or the information stored to the operand storage circuitry based on masking state data indicative of one or more masked row or column positions to be treated as representing a masking value. This is useful for improving performance of two-dimensional convolution operations, as the masking can be used to mask out selected rows or columns when performing the 2D convolution as a series of 1×1 convolution operations applied to different kernel positions.
Finite state automata that enables continuous delivery of machine learning models
A finite state automata (FSA) may comprise of a plurality of states and a plurality of events that are triggered to transition between the plurality of states to enable the continuous delivery of one or more machine learning (ML) models. Datasets may be uploaded by one or more users to a computing device. Each dataset may include columns of attributes and/or rows of data for each attribute. Each dataset may be analyzed according to respective predefined ML model criteria. Each dataset may be automatically transformed and/or enhanced to meet the predefined ML model criteria. Data analysis may be performed on each dataset to inform the building of the ML models. An algorithm may be received for each ML model. Each ML model may be built based on the respective dataset and the respective algorithm to generate an ML model file. Logs may be stored for tracking the process performed by the FSA.
Information processing apparatus, method of controlling information processing apparatus, and storage medium
An information processing apparatus includes a storage unit configured to store at least a first boot program and a second boot program corresponding to the first boot program, a controller configured to read and execute a program, detect, in accordance with occurrence of a read error at reading of the first boot program, an address of a storage area storing a program in which the read error has occurred in the first boot program, and specify, from an address of a storage area storing the second boot program, an address corresponding to the detected address. The controller reads and executes the second boot program stored in the specified address.
System and method for adapting executable object to a processing unit
Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.
Methods and apparatus to detect and annotate backedges in a dataflow graph
Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.
Object oriented smart contracts for UTXO-based blockchains
Disclosed is method and system for turning existing object-oriented programming languages into smart contract languages without introducing new syntactic features. The invented method and system provide a protocol that enables storing a history of computations on a decentralized computer network, such as UTXO-based blockchain system, for any object-oriented computer language. The invented method and system further provide for storing and updating data on blockchains, where such blockchains may be used in cryptocurrency applications and for smart contracts.
Implementing a type restriction that restricts to a non-polymorphic layout type or a maximum value
A type restriction contextually modifies an existing type descriptor. The type restriction is imposed on a data structure to restrict the values that are assumable by the data structure. The type restriction does not cancel or otherwise override the effect of the existing type descriptor on the data structure. Rather the type restriction may declare that a value of the data structure's type is forbidden for the data structure. Additionally or alternatively, the type restriction may declare that an element count allowable for a data structure's type is forbidden for the data structure. Type restriction allows optionality (where only a singleton value for a data structure is allowed), empty sets (where no value for a data structure is allowed), and multiplicity (where only a limited element count for a data structure) to be injected into a code set independent of data type. Type restriction allows certain optimizations to be performed.