The disclosed embodiments provide a mechanism to support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource.

Provided are a computer program product, system, and method for determining when to release a lock from a first task holding the lock to grant to a second task waiting for the lock. A determination is made as to whether a holding of a lock to the resource by a first task satisfies a condition and whether the lock is swappable. The lock is released from the first task and granted to a second task waiting in a queue for the lock in response to determining that the holding of the lock satisfies the condition and that the lock is swappable. The first task is indicated in the queue waiting for the lock in response to granting the lock to the second task.

A barrier synchronization circuit that performs barrier synchronization of a plurality of processes executed in parallel by a plurality of processing circuits, the barrier synchronization circuit includes a first determination circuit configured to determine whether the number of first processing circuits among the plurality of the processing circuits is equal to or greater than a first threshold value, the first processing circuits having completed the process, and an instruction circuit configured to instruct a second processing circuit among the plurality of the processing circuits to forcibly stop the process when it is determined that the number is equal to or greater than the first threshold value by the first determination circuit, the second processing circuit having not completed the process.

The techniques described herein may provide techniques to detect, categorize, and diagnose synchronization issues that provide improved performance and issue resolution. For example, in an embodiment, a method may comprise detecting occurrence of synchronization performance problems in software code, when at least some detected synchronization performance problems occur when a contention rate for software locks is low, determining a cause of the synchronization performance problems, and modifying the software code to remedy the cause of the synchronization performance problems so as to improve synchronization performance of the software code.

Disclosed is a task allocation method, apparatus, electronic device, and computer-readable storage medium. The task allocation method includes: in response to receiving a synchronization signal, determining, by the microprocessor, whether allocation of a task segment to the processing core is required according to the synchronization signal, wherein the task segment is a part of a task; in response to the allocation of the task segment to the processing core being required, instructing, by the microprocessor, to allocate the task segment to the processing core; receiving, by the processing core, the task segment; and in response to satisfying a first preset condition, sending, by the processing core, a synchronization request signal, wherein the synchronization request signal is configured to trigger the generation of the synchronization signal.

Disclosed is a task allocation method, apparatus, electronic device, and computer-readable storage medium. The task allocation method includes: in response to receiving a synchronization signal, determining, by the microprocessor, whether allocation of a task segment to the processing core is required according to the synchronization signal, wherein the task segment is a part of a task; in response to the allocation of the task segment to the processing core being required, instructing, by the microprocessor, to allocate the task segment to the processing core; receiving, by the processing core, the task segment; and in response to satisfying a first preset condition, sending, by the processing core, a synchronization request signal, wherein the synchronization request signal is configured to trigger the generation of the synchronization signal.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

An example method of reserving a resource of virtualized infrastructure in a data center on behalf of a client includes: obtaining, by a resource lock manager from a topology manager, a sub-topology for the resource from a resource topology of the virtualized infrastructure; setting, by the resource lock manager, an exclusive lock on the resource and on each of at least one descendant in the sub-topology for the resource, each exclusive lock disallowing any other lock on its respective resource; setting, by the resource lock manager, a limited lock on each ancestor in the sub-topology for the resource, each limited lock allowing any other limited lock on its respective resource; and notifying the client that a reservation of the resource is granted.

An example method of reserving a resource of virtualized infrastructure in a data center on behalf of a client includes: obtaining, by a resource lock manager from a topology manager, a sub-topology for the resource from a resource topology of the virtualized infrastructure; setting, by the resource lock manager, an exclusive lock on the resource and on each of at least one descendant in the sub-topology for the resource, each exclusive lock disallowing any other lock on its respective resource; setting, by the resource lock manager, a limited lock on each ancestor in the sub-topology for the resource, each limited lock allowing any other limited lock on its respective resource; and notifying the client that a reservation of the resource is granted.