Provided is a computer capable of reducing a diagnosis load. For each predetermined diagnosis target node among a plurality of nodes in a neural network, a determination processing unit calculates an expected output value expected as a calculation result of a node calculation process corresponding to the predetermined diagnosis target node, which is obtained when the node calculation process is executed using a predetermined input value. For each diagnosis target node, a generation processing unit generates as a diagnosis program a program for comparing the calculation result of the node calculation process corresponding to the diagnosis target node, which is obtained when the node calculation process is executed by an NN calculation processor using the input value, with the expected output value.

A method for error management is provided. The method comprises receiving a message call request regarding an error event generated by a software application. The message call request comprises a message ID associated with an error type. In response to the call request a message cache is searched for the message ID. If the ID is in the cache, an error message associated with the ID is returned. The error message provides a description of the error and suggested remedial action. If the message ID is not in the cache, the error message is fetched from a message repository that contains error messages corresponding to respective message IDs. The fetched error message is loaded into the cache and returned. Message call request data is stored in a metrics repository. The message call request data comprises frequency metrics that describe how often the message ID is received.

Systems, methods, and computer programming products for predicting, preventing and remediating failures of batch jobs being executed and/or queued for processing at future scheduled time. Batch job parameters, messages and system logs are stored in knowledge bases and/or inputted into AI models for analysis. Using predictive analytics and/or machine learning, batch job failures are predicted before the failures occur. Mappings of processes used by each batch job, historical data from previous batch jobs and data identifying the success or failure thereof, builds an archive that can be refined over time through active learning feedback and AI modeling to predictively recommend actions that have historically prevented or remediated failures from occurring. Recommended actions are reported to the system administrator or automatically applied. As job failures occur over time, mappings of the current system log to logs for the unsuccessful batch jobs help the root cause analysis becomes simpler and more automated.

In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

An information handling system includes a failsafe circuit connected to a first power control interconnect conductor, to a second power control interconnect conductor, and to a processor status interconnect conductor. A processor may provide a first level indicating an operational status of the processor to the processor status interconnect conductor when the processor is operational, and provide a second level indicating a non-operational status of the processor to the processor status interconnect conductor when the processor is non-operational. The failsafe circuit may assure, upon provision of the second level to the processor status interconnect conductor, that the first power control interconnect conductor will be in a first failsafe state and the second power control interconnect conductor will be in a second failsafe state.

Disclosed embodiments relate to adjusting vehicle Electronic Control Unit (ECU) software versions. Operations may include receiving a prompt to adjust an ECU of a vehicle from executing a first version of ECU software to a second version of ECU software; configuring, in response to the prompt and based on a delta file corresponding to the second version of ECU software, the second version of ECU software on the ECU in the vehicle for execution; and configuring, in response to the prompt, the first version of ECU software on the ECU in the vehicle to become non-executable.

The communication terminal detects a functional module of anomalous operating state, and to notify the edge server of the anomalous operating state. The edge server generates respective disk images corresponding to the functional module and a related functional module, generates a plurality of divided disk images obtained by dividing the generated disk image, and sends the plurality of divided disk images to the storage device. The storage device stores the divided disk images, and sends divided disk images corresponding to the functional module and the related functional module to the communication terminal in response to request from the communication terminal. The communication terminal generates the disk image by coupling the plurality of divided disk images acquired from the storage device, and turns on the functional module and the related functional module based on the generated disk image.

An appliance management system includes a plurality of appliances connected to a network and a portable terminal. Each of the appliances includes a sensor configured to detect an abnormality of the appliance, and a first near field wireless communication module configured to broadcast an identifier of the appliance when the sensor detects the abnormality. The portable terminal includes a second near field wireless communication module and a controller. The controller is configured to control the second near field wireless communication module to transmit an access request to an abnormal appliance upon the second near field wireless communication module receiving an identifier of the abnormal appliance. The terminal controller is also configured to control a display to display an abnormality screen including the identifier of the abnormal appliance upon the second near field wireless communication module receiving abnormality information from the abnormal appliance.

A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.

An integrated circuit (IC) device for detecting errors within a register, the IC device includes registers and parity checking circuitry. The parity checking circuitry is coupled to the registers and comprises a first parity circuitry, a second parity circuit, and error detection circuitry. The first parity circuit receives first register values from the registers and determine a first value from the first register values. The second parity circuit is receives second register values from the registers and determines a second value from the second register values. The error detection circuitry compares the first value and the second value to detect a first error within the registers, and output an error signal indicating the first error.