User data units are received at a memory controller to be written to a RAID strip in non-volatile memory. A first parity value is calculated for the user data units using a first parity calculation. A second parity value different from the first parity value is also calculated for the plurality of user data units using a second parity calculation. The first parity value is stored in a first parity data unit in the non-volatile memory and the second parity value is stored in a second parity data unit in the non-volatile memory. Recovery from a failure of up to two data units thus enabled by recalculating the value of the failed data units based on one or more of the first parity data unit, the second parity data unit, and the values of other user data units of the plurality of data units.

A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an i.sup.th operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the i.sup.th operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an i.sup.th operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the i.sup.th operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

The embodiments of the present application provide a polar code construction method and apparatus, which relate to the field of communications technology. The method comprises: obtaining a polar weight spectrum for each polarized channel; calculating an upper bound of error probability of each polarized channel based on the obtained polar weight spectrum, distribution probability density of a fading factor of a fading channel, and a signal-to-noise ratio of the fading channel; taking a logarithm of the calculated upper bound of the error probability for each polarized channel and obtaining a reliability metric of the polarized channel based on the taken logarithm, wherein the smaller the metric value is, the higher the reliability of the polarized channel is; sorting all polarized channels in an ascending order of the reliability metric and selecting part of the polarized channels having a lowest reliability metric for transmitting information bits and the remaining polarized channels for transmitting frozen bits. According to the embodiments of the present application, performing polar code construction under the condition of a fading channel can improve the efficiency of polar code construction.

A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information.

Redundancy information can be included in nucleotide symbol strings encoding underlying data. To avoid propagation of errors during the decoding process, during encoding, a constrained encoding can be performed before the redundancy information is computed. The redundancy information can be an outer encoding across multiple nucleotide symbol strings. An inner coding within nucleotide symbol strings can also be supported. Such redundancy information can be interleaved into the underlying nucleotide symbol strings to which the constrained encoding has been applied, resulting in a relaxed constraint. Insertion/deletion redundancy information can also be included in the resulting strings, and an insertion/deletion-sensitive sequence can be included to assist in recovering accurate sequences during decoding operations.

A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information.

A computer-implemented method according to one embodiment includes, prior to an execution of a deterministic program, determining a pre-computed check sequence for a first plurality of values associated with the execution of the deterministic program, during the execution of the deterministic program, determining a runtime check sequence for a second plurality of values associated with the execution of the deterministic program, comparing the pre-computed check sequence to the runtime check sequence; and identifying one or more errors associated with the execution of the deterministic program, based on the comparing.

A computer-implemented method according to one embodiment includes, prior to an execution of a deterministic program, determining a pre-computed check sequence for a first plurality of values associated with the execution of the deterministic program, during the execution of the deterministic program, determining a runtime check sequence for a second plurality of values associated with the execution of the deterministic program, comparing the pre-computed check sequence to the runtime check sequence; and identifying one or more errors associated with the execution of the deterministic program, based on the comparing.