Patent classifications
G06F11/085
Hierarchical buffering scheme to normalize non-volatile media raw bit error rate transients
A computer-implemented method for writing data to a first media using a set of data structures to reduce potential errors when reading the data from the first media is described. The method includes writing, user data to a set of memory cells in the first media; and storing, in response to writing the user data to the set of memory cells, a first set of parity bits associated with the user data in a first buffer that is held within a second media separate from the first media and is a different type than the first media, wherein the first set of parity bits provide error correction information for correcting errors introduced to the user data while stored in the set of memory cells or read from the set of memory cells.
MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.
MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.
MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.
Memory system and operating method thereof
A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.
Method and Device for Processing Data via Coded Operations
A computer program product, a device, a functionally secure programmable controller and a method for processing data via coded operations in a number of cycles, wherein an uncoded variable x is coded with a cycle-specific signature D and a variable-specific signature B.sub.x to form a coded variable x.sub.c in accordance with the relationship: x.sub.c=D.Math.x+B.sub.x.
Method and Chip for Cyclic Code Encoding, Circuit Component, and Electronic Device
According to embodiments of the present disclosure, a method and a chip for cyclic code encoding, a circuit component, and an electronic device are provided. The method includes: generating, based on a first symbol sequence related to a first part of symbols in the K payload symbols, a first parity sequence corresponding to the first symbol sequence; generating, based on a second symbol sequence related to a second part of symbols in the K payload symbols, a second parity sequence corresponding to the second symbol sequence, where the first part of symbols are different from the second part of symbols; generating the (NK) parity symbols based on the first parity sequence and the second parity sequence.
ERASURE CODING MAGNETIC TAPES FOR MINIMUM LATENCY AND ADAPTIVE PARITY PROTECTION FEEDBACK
A magnetic tape device or system can store erasure encoded data that generates a multi-dimensional erasure code corresponding to an erasure encoded object comprising a code-word (CW). The multi-dimensional erasure code enables using a single magnetic tape in response to a random object/file request, and correct for an error within the single magnetic tape without using other tapes. Encoding logic can further utilize other magnetic tapes to generate additional parity tapes that recover data from an error of the single magnetic tape in response to the error satisfying a threshold severity for a reconstruction of the erasure coded object or chunk(s) of the CW. The encoding logic can be controlled, at least in part, by one or more iterative coding processes between multiple erasure code dimensions that are orthogonal to one another.
METHOD AND APPARATUS FOR STORING BLOCKCHAIN DATA BASED ON ERROR CORRECTION CODE
Disclosed herein are a method and an apparatus for storing blockchain data based on error correction code. The method for storing blockchain data based on error correction code includes dividing block data to be stored into multiple subblock datasets, generating parity datasets corresponding to the block data, and storing the subblock datasets and the parity datasets in proportion to storage capacities of the blockchain data storage nodes.
HIERARCHICAL BUFFERING SCHEME TO NORMALIZE NON-VOLATILE MEDIA RAW BIT ERROR RATE TRANSIENTS
A computer-implemented method for writing data to a first media using a set of data structures to reduce potential errors when reading the data from the first media is described. The method includes writing, user data to a set of memory cells in the first media; and storing, in response to writing the user data to the set of memory cells, a first set of parity bits associated with the user data in a first buffer that is held within a second media separate from the first media and is a different type than the first media, wherein the first set of parity bits provide error correction information for correcting errors introduced to the user data while stored in the set of memory cells or read from the set of memory cells.