According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.

A semiconductor system includes a process control circuit configured to determine whether to perform a patrol training operation, generate a voltage code signal for adjusting a level of a reference voltage which determines a logic level of data in a target memory circuit, and adjust the voltage code signal on the basis of a fail information signal corresponding to the target memory circuit, an operation control circuit configured to receive a command and an address from a host, generate, from the command, a write signal and a read signal for performing a normal operation, and generate, from the address, an internal address for performing the normal operation and an error detection circuit configured to detect an error in the data by receiving the data from the target memory circuit, and generate the fail information signal depending on whether the error has occurred in the data.

A system includes a memory device storing groups of managed units and a processing device operatively coupled to the memory device. The processing device is to, during power on of the memory device, perform including: causing a read operation to be performed at a subset of a group of managed units; determining a bit error rate related to data read from the subset of the group of managed units; and in response to the bit error rate satisfying a threshold criterion, causing a rewrite of the data stored at the group of managed units.

Methods, systems, and devices for techniques for memory error correction are described. A memory device may operate cycles associated with refresh operations and cycles associated with refresh with error correction (ECC) operations independently. For example, the memory device may include an ECC patrol block having an error correction counter which indicates a row on which to perform an error correction procedure. Additionally, the memory device may include a refresh counter which indicates a row on which to perform a refresh operation. In response to receiving a command of a first, the memory device may modify the error correction counter and maintain the refresh counter. Alternatively, in response to receiving a command of a second, the memory device may modify the refresh counter and maintain the error correction counter.

A storage system comprises a non-volatile memory configured to store boot code and a control circuit connected to the non-volatile memory. In response to a first request from a host to transmit the boot code, the storage system commences transmission of the boot code to the host at a first transmission speed. Before successfully completing the transmission of the boot code to the host at the first transmission speed, it is determined the boot code transmission has failed. Therefore, the host will issue a second request for the boot code. In response to the second request for the boot code, and recognizing that this is a fallback condition because the previous transmission of the boot code failed, the storage apparatus re-transmits the boot code to the host at a lower transmission speed than the first transmission speed.

A solid state drive (SSD) includes a first storage region classified as byte addressable NV storage region and a controller communicatively coupled to the first storage region by a bus. The controller detects a reduced storage capacity of the first storage region, and in response to the detection, reclassifies the first storage region as a block addressable NV storage region. The SSD dynamically changes byte addressable NV storage regions to block addressable NV storage regions as the byte addressable NV storage regions are degraded, thereby extending the longevity of the SSD.

Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

Embodiments combine error correction code (ECC) and transparent memory built-in self-test (TMBIST) for memory fault detection and correction. An ECC encoder receives input data and provides ECC data for data words stored in memory. Input XOR circuits receive the input data and output XOR'ed data as payload data for the data words. Output XOR circuits receive the payload data and output XOR'ed data. An ECC decoder receives the ECC data and the XOR'ed output data and generates error messages. Either test data from a controller running a TMBIST process or application data from a processor executing an application is selected as the input data. Either test address/control signals from the controller or application address/control signals from the processor are selected for memory access. During active operation of the application, memory access is provided to the processor and the controller, and the memory is tested during the active operation.

Techniques for using erasure coding in a single region to reduce the likelihood of losing objects in a cloud object storage platform are provided. In one set of embodiments, a computer system can upload a plurality of data objects to a region of a cloud object storage platform, where the plurality of data objects including modifications to a data set. The computer system can further compute a parity object based on the plurality of data objects, where the parity object encodes parity information for the plurality of data objects. The computer system can then upload the parity object to the same region where the plurality of data objects was uploaded.

A method and apparatus for calibrating read threshold for cells of a target wordline (WL) that may be conducted on a die, in a controller connected to a memory die, or both. Voltage values of one or more adjacent WL cells are read, and based on the voltage values of the adjacent cells, cells of the target WL are grouped. A read threshold calibration is carried out on each group. The calibration thresholds are then used for read operations on the cells of each distinct group of the target WL.