Systems and methods for logically organizing data for storage and recovery on a data storage medium using a multi-level format are described. Embodiments include systems and methods for protecting data stored on a data storage medium so that the data may be recovered without errors.

Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

An apparatus comprises a memory and a controller. The memory generally comprises a plurality of memory modules, each having a size less than a total size of the memory and configured to store data. The controller may be configured to process a plurality of read/write operations, classify data pages from multiple blocks of the memory as hot-read data or non hot-read data, and aggregate the hot-read data by selecting one or more of the hot-read data pages from multiple memory blocks and mapping the selected hot-read data pages to dedicated hot-read data blocks using a strong type of error correcting code during one or more of a garbage collection state, a data recycling state, or an idle state. The aggregation of the hot-read data pages and use of the strong type of error correcting code reduces read latency of the hot-read data pages, reduces a frequency of data recycling of the hot-read data pages, and reduces an impact of read disturbs on endurance of the memory.

Disclosed embodiments include a memory device having a memory array that includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line and a sense amplifier that includes first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type, a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line, and a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line.

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages a plurality of namespaces for storing a plurality of kinds of data having different update frequencies. The controller encodes write data by using first coding for reducing wear of a memory cell to generate first encoded data, and generates second encoded data to be written to the nonvolatile memory by adding an error correction code to the first encoded data. The controller changes the ratio between the first encoded data and the error correction code based on the namespace to which the write data is to be written.

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

A first node group including at least three nodes is predefined in a distributed storage system. Each node of the first node group is configured to send data blocks stored in storage devices managed by the node to other nodes belonging to the first node group. A first node is configured to receive data blocks from two or more other nodes in the first node group. The first node is configured to create a redundant code using a combination of data blocks received from the two or more other nodes and store the created redundant code to a storage device different from storage devices holding the data blocks used to create the redundant code. Combinations of data blocks used to create at least two redundant codes in redundant codes created by the first node are different in combination of logical addresses of constituent data blocks.

Writing time is shortened even in a memory writing time for each access unit is not constant. A writing time prediction information holding unit holds writing time prediction information for predicting the writing time in a plurality of memory modules for each of a plurality of memory modules. A request selecting unit preferentially selects a write request of which longer writing time is predicted out of a plurality of write requests requiring writing in each of a plurality of memory modules on the basis of the writing time prediction information.

A device includes an interface configured to connect to a communication link. A controller of the device is configured to generate a redundancy code using first data and second data, and to transmit the redundancy code together with the first data to the interface.

A device includes an interface configured to connect to a communication link. A controller of the device is configured to generate a redundancy code using first data and second data, and to transmit the redundancy code together with the first data to the interface.