Patent classifications
G06F11/1402
DATA ASSET RECONSTRUCTION
According to an aspect, data asset reconstruction includes receiving a data lineage for a data asset, where the data lineage identifies a data source connected to the data asset by an intermediate process. It is determined whether the intermediate process can be used to reconstruct a lost data asset. Based on determining that the intermediate process can be used to reconstruct the lost data asset, reconstructing the lost data asset with the intermediate process and the data source.
Flit-based parallel-forward error correction and parity
A flit-based packetization approach is used for transmitting information between electronic components. A protocol stack can generate transaction layer packets from information received from a transmitting device, assemble the transaction layer packets into one or more flits, and protect the flits with a flit-level cyclic redundancy check (CRC) scheme and a flit-level forward error correction or parallel-forward error correction (FEC) scheme. Flit-level FEC schemes can provide improved latencies and efficiencies over per-lane FEC schemes. To improve retry probability, flits can contain information indicating whether immediately preceding flits are null flits. Receivers can avoid sending a retry request for a corrupted flit if a seceding flit indicates the corrupted flit is a null fit. Parity flits can be used to protect groups of flits and correct single-flit errors.
Method for accessing flash memory module, associated flash memory controller and electronic device for accelerating reading speed of flash
The present invention provides a method for accessing a flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, each clock includes a plurality of pages, and the method includes the steps of: providing a read-retry table, wherein the read-retry table includes a plurality of read setting levels, each read setting level corresponds to at least one read voltage, and no two read setting levels have the same read voltage; establishing a read success recording table, which records at least one specific read setting level that was previously used to successfully read the flash memory module; and when it is required to the read the flash memory module, using the at least one specific read setting level recorded in the read success recording table to read the flash memory module.
INFORMATION PROCESSING APPARATUS, STORAGE APPARATUS, AND INFORMATION PROCESSING SYSTEM
An information processing apparatus includes a memory and a processor configured to obtain information on a relation between virtual volumes used by a virtual machine and physical volumes provided in a storage apparatus from a management machine configured to manage allocations of the virtual volumes to the physical volumes; store the obtained information into a management information stored in the memory; and in response to receiving a copy request, obtain information on a first physical volume allocated to the first virtual volume designated as a copy participant in the copy request from the management information when the information on the first virtual volume is present in the management information, and send the storage apparatus a copy instruction designating the first physical volume as a copy participant. Obtain the information on the relation is performed when the information on the first virtual volume is not present in the management information.
Synchronization policies among nodes
Services associated with first and second nodes are managed. As part of the management, the first node receives a request to modify the services. A synchronization policy is identified. The synchronization policy requires that modifications attempted on the set of services on the first node also be attempted on the second node. In response to the request, an attempt is made to modify the set of services on the first node. Further, in response to the request and pursuant to the synchronization policy, the second node is caused to attempt to modify the set of services. The synchronization policy is identified as a relaxed synchronization policy. A determination is made that the attempt to modify the set of services on the second node failed. Based on identifying that the synchronization policy is a relaxed synchronization policy, the attempt to modify the set of services on the first node continues.
Processing system, related integrated circuit, device and method
In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
Method for gracefully handling QAT hardware or CPU software failures by dynamically switching between QAT hardware and CPU software for data compression and decompression
A method, apparatus, and system for handling a failure of a hardware cryptography/compression accelerator is disclosed. The operations comprise: detecting that a hardware cryptography/compression accelerator at a first data storage system has failed; determining one or more failed cryptography and/or compression operation tasks that were submitted to the hardware cryptography/compression accelerator but were not completed due to the failure of the hardware cryptography/compression accelerator; and performing a remedial operation in response to the hardware cryptography/compression accelerator failure to prevent a systemic failure.
Cumulative backups
In one example, a method includes performing various operations at a backup server. These operations may include receiving, from a node, a request for restoration of a cumulative backup that includes a plurality of partial backups that have been merged together, where the plurality of partial backups includes data from a group of one or more nodes, and the group includes the node. The method further includes checking the cumulative backup to determine whether or not the cumulative backup has been finalized, accessing the cumulative backup when it has been determined that the cumulative backup has been finalized, and restoring the cumulative backup to a target node.
Point-in-time snap copy withdrawal management
Withdrawal of a point-in-time snap copy relationship or a portion of such a relationship, is managed in a manner which can obviate disruption of consistency groups due to the withdrawal. If the withdrawal request is directed to a subrange of the original snap copy relationship, the snap copy relationship is split by creating one or more point-in-time snap copy relationships over one or more subranges of tracks of the snap copy source. A determination is made as to whether to delay execution of the withdrawal request to temporarily preserve data of the withdrawal range. Disruptions to completion of consistency groups may be avoided by selectively delaying the withdrawal of a snap copy relationship corresponding to the withdrawal subrange. In so far as the host is involved, a host may treat the withdrawal request as immediately granted without delay. Other aspects may be realized, depending upon the particular application.
Controller that receives a cyclic redundancy check (CRC) code for both read and write data transmitted via bidirectional data link
A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.