A method for operating a microcontroller, which includes a processor and a peripheral circuit on a common chip, the method including initiating a process in the peripheral circuit, in the peripheral circuit generating recovery data, executing the process, checking whether the process has been executed successfully and, in the event that the check reveals that the process has not been executed successfully, generating recovered data from the recovery data, and executing the process again.

Micro-architectural fault detectors are described. An example of storage mediums includes instructions for receiving one or more micro instructions for scheduling in a processor, the processor including one or more processing resources; and performing fault detection in performance of the one or more micro instructions utilizing one or more of a first idle canary detection mode, wherein the first mode includes assigning at least one component as an idle canary detector to perform a canary process with an expected outcome, and a second micro-architectural redundancy execution mode, wherein the second mode includes replicating a first micro instruction to generate micro instructions for performance by a set of processing resources.

Methods, systems, and apparatuses related to multiple instructions sets or redundant instructions for memory access and management. In one approach, a controller of the memory device provides a first set of functions for management of a storage media of the memory device. The controller uses the first set of functions to service one or more requests received from the host device. The controller provides a second set of functions for management of the storage media. The second set includes one or more functions that are redundant to the first set. When a request is received from the host device, in response to determining that the first set of functions is unavailable to service the request, the controller services the request using one or more of the redundant functions of the second set.

A system, method, and computer readable medium for asynchronous live migration of applications between two or more servers. The computer readable medium includes computer-executable instructions for execution by a processing system. Primary applications runs on primary hosts and one or more replicated instances of each primary application run on one or more backup hosts. Asynchronous live migration is provided through a combination of process replication, logging, barrier synchronization, checkpointing, reliable messaging and message playback. The live migration is transparent to the application and requires no modification to the application, operating system, networking stack or libraries.

An apparatus comprising data processing circuitry for processing data in one of a plurality of operating states, an instruction decoder for decoding instructions and error checking circuitry for performing error checking operations. In response to a touch instruction being decoded by the instruction decoder, error checking operation is performed on selected architectural state. The architectural state is architecturally inaccessible to the operating state. As a result of the touch instruction, the architectural state remains unchanged, at least when no error is detected.

A system for code development and execution includes a client interface and a client processor. The client interface is configured to receive user code for execution and receive an indication of a server that will perform the execution. The client processor is configured to parse the user code to identify one or more data items referred to during the execution. The client processor is also configured to provide the server with an inquiry for metadata regarding the one or more data items, receive the metadata regarding the one or more data items, determine a logical plan based at least in part on the metadata regarding the one or more data items; and provide the logical plan to the server for execution.

A method, apparatus, and system for handling a failure of a hardware cryptography/compression accelerator is disclosed. The operations comprise: detecting that a hardware cryptography/compression accelerator at a first data storage system has failed; determining one or more failed cryptography and/or compression operation tasks that were submitted to the hardware cryptography/compression accelerator but were not completed due to the failure of the hardware cryptography/compression accelerator; and performing a remedial operation in response to the hardware cryptography/compression accelerator failure to prevent a systemic failure.

An FPGA includes a CRAM that records configuration data for defining a circuit configuration, a main circuit unit of which the circuit configuration is determined according to the configuration data, and an error detection unit that executes memory check processing of detecting whether or not any error is present in the configuration data. A control unit causes the main circuit unit to sequentially execute a plurality of sub-processing steps obtained by segmenting predetermined processing upon receiving a query requesting execution of the predetermined processing to execute the predetermined processing and enables the error detection unit to execute the memory check processing for each of the sub-processing steps.

Herein is disclosed an integrated input/output (I/O) processing system, comprising an I/O port, configured to receive I/O data and to deliver the I/O data to one or more processors; one or more processors, further comprising a first processing logic and a second processing logic, wherein the one or more processors are configured to deliver the received I/O data to the first processing logic and to the second processing logic, and wherein the first processing logic and the second processing logic are configured to redundantly process the I/O data; and a comparator, configured to compare an output of the first processing logic and an output of the second processing logic.

A graphics processing system configured to use a rendering space which is subdivided into a plurality of tiles to render a scene that includes safety-critical elements of geometry, the graphics processing system being configured to: receive elements of geometry of the scene to be rendered, one or more of the elements of geometry being a safety-critical element of geometry; process elements of geometry, in a geometry processing phase, so as to form, for each tile of the rendering space, a respective tile list indicating the elements of geometry included in that tile; and for each of a plurality of the tiles, process elements of geometry in the tile, in a fragment processing phase, so as to generate a respective fragment-processed output; wherein the graphics processing system comprises a controller configured to: cause a set of one or more safety-critical elements of geometry to be processed in the geometry processing phase; identify as protected tiles one or more tiles for which the corresponding one or more tile lists are modified due to processing the set of one or more safety-critical elements of geometry in the geometry processing phase; cause each of the protected tiles to be processed first and second times in the fragment processing phase so as to, respectively, generate first and second fragment-processed outputs; and raise a fault signal if the first and second fragment-processed outputs of a protected tile do not match.