A clock signal in a device may be switched to a fallback clock signal if a clock fault is detected. One or more subsystem clock signals provided to one or more subsystems of the device may be monitored. If a fault associated with a clock signal is detected, then a fallback clock signal may be provided to the subsystem in place of the subsystem clock signal.

An apparatus can include an interface circuit configured to receive an operating parameter and a control circuit coupled to the interface circuit and configured to store the operating parameter. The apparatus also can include a clock error detection circuit coupled to the control circuit. The clock error detection circuit can be configured to detect a clock error condition on a clock signal based upon the operating parameter and, responsive to detecting the clock error condition, generate a signal indicating an occurrence of the clock error condition.

A frequency converter control unit has: a serial control unit interface, a control unit clock pulse generator for generating a control unit clock pulse, and a control unit processor which is designed to define a control parameter depending on an actual value. A power unit has a data connection to the control unit and has several power semiconductors, a power unit clock pulse generator for generating an adjustable power unit clock pulse, a serial power unit interface, a clock pulse generator adjustment unit which has a signal connection to the power unit interface and which adjusts the power unit clock pulse depending on signals received by the power unit on the power unit interface, a power unit processor which controls the power semiconductors depending on the control parameter and the power unit clock pulse, and a sensor unit that determines the actual value. The control unit transmits the control parameter via the control unit interface to the power unit. The power unit transmits the actual value via the power unit interface to the control unit.

An input and output module transmits and receives data via a data line. The input and output module includes a protocol machine for a security protocol for data transfer and a clock. The protocol machine and instructions for clock processing are stored as sequence control in a read-only memory of the input and output module.

A semiconductor integrated circuit device comprises a first oscillation circuit which is supplied with an external DC power and generates a first clock, a power supply circuit which is supplied with the external DC power and outputs a DC voltage by a switching operation based on the first clock, a second oscillation circuit which generates a second clock, a load circuit which is supplied with the output DC voltage and operates based on the second clock, a monitor which monitors an operation of the first oscillation circuit based on the second clock under a state that the first and second oscillation circuits are in operation, and a switch circuit which switches to supply the power supply circuit with the second clock in place of the first clock when the monitor circuit detects a failure of the first oscillation circuit.

A signal processing apparatus includes an oscillation circuit, an interpolation circuit, a matching filter, a high-pass filter and a timing recovery circuit. The oscillation circuit generates a clock signal. The interpolation circuit performs interpolation on an input signal according to the clock signal to generate an interpolation sample result. The matching filter demodulates the interpolation sample result to generate an output signal. The high-pass filter performs high-pass filtering on the interpolation sample result to generate a filtered result. The timing recovery circuit receives the filtered result, and performs timing recovery according to the filtered result.

A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock input using the reference clock input, which is compared to a threshold. The control logic determines whether the measurement exceeded the threshold and, based on the measurement exceeding the threshold, cause generation of another measurement of a frequency or a duty cycle using the third clock input in combination with the first clock input or the reference clock input. The control logic may determine whether the other measurement exceeded a threshold and, based on such a determination, further determine that the test clock input or the reference clock input are faulty.

A clock generation circuit and a clock signal generation method are disclosed. In the method, a direct current bias circuit in a first clock source superimposes a first direct current voltage on a first clock signal output by a first oscillation circuit, to generate a second clock signal; and a logical operation is performed on the second clock signal and a third clock signal that is generated by a second clock source, to generate a fourth clock signal. The fourth clock signal is used as a signal output by a clock generation circuit. In the method, when the first oscillation circuit cannot normally work, the clock generation circuit can still output a correct clock signal. This avoids clock signal interruption when switching is performed from the first clock source to the second clock source.

A method for monitoring a clock generator module of an electronic circuit which is configured to generate a plurality of clock signals for the electronic circuit. A monitoring module external to the circuit alternately causes the selection of one of the clock signals in the circuit as a selection signal; wherein based on the selection signal a PWM signal, whose period duration and holding time are predetermined, is generated and output; wherein the PWM signal is received from the electronic circuit by the monitoring module and measured using a monitoring clock signal to determine at least one measurement result, the at least one measurement result is compared with at least one comparison result or comparison result range, and a malfunction of the clock generator module is determined if the at least one measurement result does not match the at least one comparison result or comparison result range.

The memory device includes a clock receiver receiving an external clock signal, a transmitter receiving first to Nth data in parallel and sequentially outputting the first to Nth data based on first to Nth clock signals including different phases, and a QEC circuit correcting a skew between the first to Nth clock signals, wherein the external clock signal includes a same frequency as the first to Nth clock signals, and the QEC circuit selectively receives the first clock signal among the first to Nth clock signals, generates the second clock signal including a phase different from a phase of the first clock signal based on a delay operation with respect to the first clock signal, and corrects the skew between the first to Nth clock signals by performing a phase comparison between the first to Nth clock signals generated based on the first and second clock signals.