The present disclosure provides a redundancy method for a flash memory device. The flash memory device comprises multiple storage areas in which at least one storage area is configured as a temporary storage area for redundant operations. The method comprises: performing redundant operations to a first set of pages stored in one of the plurality of storage areas in a cache to generate an intermediate result; storing the intermediate result to the storage area of the at least one temporary storage area for redundant operation from the cache; performing redundant operations to the (m+1)th set of pages stored in one storage area the redundant operation result of and the first set of pages stored in the at least one temporary storage area for redundant operation to produce a final result in the cache; storing the final result to the corresponding pages in the (m+1)th set of pages from the cache.

Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well. The safety mechanisms cover data stream fault detection, software defined redundant allocation, cluster interlayer safety, cluster intralayer safety, layer control unit (LCU) instruction addressing, weights storage safety, and neural network intermediate results storage safety.

A clock fractional divider module which is formed as, comprises or has integrated therein a dual-core lock step unit. The dual-core lock step unit is configured in order to realize a clock fractional division arrangement, mechanism or process accompanied by an error detection, recognition and/or correction arrangement, mechanism or process.

A processor system comprises at least a program counter structure, an interrupt control device, a memory, and an apparatus. The interrupt control device is configured to respond to an interrupt request by providing the program counter structure with an address associated with the interrupt request. The program counter structure is configured to output the address to the memory via a memory interface. The apparatus is configured to protect the program counter structure in case of an interrupt request, the apparatus includes an interface, a comparing device, and an outputting device.

In certain aspects, a device comprises a first processing unit; a first power distribution network coupled to the first processing unit; a first decoupling capacitor coupled to the first power distribution network; a second processing unit configured to be identical to the first processing unit; a second power distribution network coupled to the second processing unit; and a second decoupling capacitor coupled to the second power distribution network, wherein the second decoupling capacitor is configured to have different effect on the second power distribution network than the first decoupling capacitor on the first power distribution network.

A method for tracing an error of a logic system design includes obtaining an assertion failure of a combinational cone of the logic system design, the combinational cone including a plurality of sub-cones; and obtaining machine learning models of the sub-cones. Each sub-cone represents a sub-circuitry of the logic system design and has one or more input signals and an output signal. The assertion failure indicates an actual signal value of the combinational cone at a current clock cycle being different from an expected output value at the current clock cycle. The method also includes: performing backtracing on the sub-cones according to the assertion failure, the machine learning models of the sub-cones, and dynamic backtracing sensitivities corresponding to the sub-cones, to obtain a backtracing result; and outputting one or more target sub-cones as candidate root causes of the assertion failure according to the backtracing result.

A failure prediction apparatus includes a memory and a processor coupled to the memory. The processor acquires a score based on an output of each of a plurality of sensors associated with each of a plurality of circuit arrangement regions, in each of the plurality of circuit arrangement regions a logic circuit constructed by programming is arrangeable, and performs a process of making a determination on a possibility of an occurrence of a failure with respect to each of the plurality of circuit arrangement regions based on the score for each of the circuit arrangement regions.

The present disclosure provides a redundancy method for a flash memory device. The flash memory device comprises multiple storage areas in which at least one storage area is configured as a temporary storage area for redundant operations. The method comprises: performing redundant operations to a first set of pages stored in one of the plurality of storage areas in a cache to generate an intermediate result; storing the intermediate result to the storage area of the at least one temporary storage area for redundant operation from the cache; performing redundant operations to the (m+1)th set of pages stored in one storage area the redundant operation result of and the first set of pages stored in the at least one temporary storage area for redundant operation to produce a final result in the cache; storing the final result to the corresponding pages in the (m+1)th set of pages from the cache.

An abnormality determination means performs detection of abnormality of one of the pairs of detection means at a normal speed, and performs detection of abnormality of the other of the pairs at a speed not higher than the normal speed, and, when a sign of abnormality of the detection means is detected at the normal speed, a CPU performs switching to the other normal pair and continues control, and the abnormality determination means performs detection of abnormality of the other normal pair at the normal speed, and meanwhile, continues to perform detection of abnormality of the abnormal pair at a speed not higher than the normal speed.

Methods and apparatus for detecting that a processing node, in a network including a plurality of processing nodes, is reporting invalid results and for taking corrective actions in response to the detection are described.