Methods and systems for enhanced data reliability for sensor devices, such as Internet of Things (IoT) sensors can include a first set of sensor devices (e.g., primary sensors) for collecting data in accordance with an application program. A second set of sensor devices (peer sensors) can be enabled for collecting supplemental data. Each of the sensor devices in the second set of sensor devices corresponds to one of the sensor devices in the first set of sensor devices. After receiving data from a selected sensor device of the set of first sensor devices and determining that the received data triggers a notification for a critical event, a second sensor of the second set of sensor devices can be interrogated to confirm the critical event. The event is confirmed by a convergence of data from the selected sensor device and the supplemental data from the second sensor device.

An improved method for investigating a functional behavior of a component of a technical installation includes comparing a signal of the component to be investigated and representing the functional behavior of the component with a reference signal which describes an average functional behavior of identical components. During the comparison, a comparison variable describing the deviation of the signal from the reference signal is determined. In addition, a probability of the occurrence of the comparison variable is determined by using a predefinable distribution of a multiplicity of such comparative variables. A computer program and a computer readable storage medium are also provided.

There is a need to detect faults on a path between a memory access circuit and a shared resource, faults in a logic circuit, and faults in the shared resource. A semiconductor device includes: a first memory access circuit; a second memory access circuit to check the first memory access circuit; a memory that outputs a memory address based on a first access address input from the first memory access circuit; a duplexing comparison circuit that compares the first access address with a second access address output from the second memory access circuit; a first address comparison circuit that compares the first access address with the memory address; and an error control circuit that outputs a control signal based on a comparison result from the duplexing comparison circuit and a comparison result from the first address comparison circuit.

An apparatus 2 comprises at least three processing circuits 4 to perform redundant processing of a common thread of program instructions. Error detection circuitry 16 is provided comprising a number of comparators 22 for detecting a mismatch between signals on corresponding signal nodes 20 in the processing circuits 4. When a comparator 22 detects a mismatch, this triggers a recovery process. The error detection circuitry 16 generates an unresolvable error signal 36 indicating that a detected area is unresolvable by the recovery process when, during the recovery process, a mismatch is detected by one of the proper subset 34 of the comparators 22. By considering fewer comparators 22 during the recovery process than during normal operation, the chances of unrecoverable errors being detected can be reduced, increasing system availability.

A field programmable gate array (FPGA) including a root of trust architecture. The architecture includes a system controller providing system control commands for the architecture and a cryptography processor for performing a hash or key operation for authentication of controller-embedded software and attestation of correct firmware in external system resources. The architecture also includes a lock-step fault-tolerant processor being responsive to messages from the system controller, and including a plurality of soft lock-step cores. Each soft core including separate memory and resources and operating on the same input, where each soft core provides output messages that are analyzed by a logic in the fault-tolerant processor that selects one of the messages to be output to the cryptography processor.

Operational faults, including transient faults, are detected within computing hardware for mission-critical applications. Operational requests received from a requestor node are to be processed by shared agents to produce corresponding responses. A first request is duplicated to be redundantly processed independently and asynchronously by distinct shared agents to produce redundant counterpart responses including a first redundant response and a second redundant response. The first redundant response is compared against the second redundant response. In response to a match, the redundant responses are merged to produce a single final response to the first request to be read by the requestor node. In response to a non-match, an exception response is performed.

A safety-relevant computer system, in particular a railway safety system, contains at least two hardware channels. A memory check results of the channels are fed to at least one comparator, which triggers an error response if the memory check results are not equal. In order to be able to use diverse software programs created by compilers, memory check results of the diverse software programs of each channel are fed to the comparator. The memory check results of a first software program of the first and second channels are compared with each other and the memory check results of a second software program of the first and second channels are compared with each other.

A failure prediction apparatus includes a memory and a processor coupled to the memory. The processor acquires a score based on an output of each of a plurality of sensors associated with each of a plurality of circuit arrangement regions, in each of the plurality of circuit arrangement regions a logic circuit constructed by programming is arrangeable, and performs a process of making a determination on a possibility of an occurrence of a failure with respect to each of the plurality of circuit arrangement regions based on the score for each of the circuit arrangement regions.

Executing critical and non-critical sections of program code include executing a non-critical section of a first program by a first processor and executing a non-critical section of a second program by a second processor. The first processor signals the second processor with context to commence redundant execution of the critical section. The second processor switches from executing the second program to executing the critical section of the first program. The first processor executes the critical section of the first program concurrent with the second processor.

A semiconductor device is provided with normal memory cells constituted so as to store user data, reference memory cells constituted so as to generate a reference signal for reading out the normal memory cells, and a control circuit that carries out a defect detecting operation for detecting whether or not the reference memory cell and data stored in the reference memory cell are coincident with expected values on the stored data read out from the reference memory cells. Moreover, it is also provided with a control circuit for executing a defect correcting operation for correcting data to be stored in the reference memory cells that are detected as defective. Furthermore, it is also provided with a control circuit that is configured so as to cut off the reference memory cell detected as defective from the sense amplifier.