An information processing system includes a first determining unit, a second determining unit, and a processing unit. The first determining unit determines a result indicating a second fixed state for data when a first condition is satisfied, the first condition indicating that t2 or more results of a first recommended state or a first fixed state are selected for the same data. The second determining unit determines the result indicating the first fixed state for the data when a second condition is satisfied, the second condition indicating that t1 or more results indicating the second fixed state are selected for the same data. The second determining unit also determines the result indicating the first recommended state for the data when a third condition is satisfied, the third condition indicating that (b+1) or more results indicating the second fixed state are selected for the same data.

A host central processing unit subsystem that writes information to external memory may provide policy to the external memory. Then every time a write comes from the host subsystem, a memory controller within the memory may check the write against the policy stored in the memory and decide whether or not to implement the write.

There is a need to detect faults on a path between a memory access circuit and a shared resource, faults in a logic circuit, and faults in the shared resource. A semiconductor device includes: a first memory access circuit; a second memory access circuit to check the first memory access circuit; a memory that outputs a memory address based on a first access address input from the first memory access circuit; a duplexing comparison circuit that compares the first access address with a second access address output from the second memory access circuit; a first address comparison circuit that compares the first access address with the memory address; and an error control circuit that outputs a control signal based on a comparison result from the duplexing comparison circuit and a comparison result from the first address comparison circuit.

In a data processing device including two sets of circuit pairs which are respectively duplicated in two clock domains which are asynchronous to each other, an asynchronous transfer circuit that transfers a payload signal is provided between the two sets of circuit pairs. The asynchronous transfer circuit includes two sets of a pair of bridge circuits which are respectively connected to the two sets of circuit pairs, and asynchronously transfers the payload signal and a control signal indicating a timing at which the payload signal is stable on a reception side. The two sets of a pair of bridge circuits and the payload signals can be duplicated, but the control signal is not duplicated, and the received payload signal is used for timing control to supply an expected same time difference, to the pair of duplicated circuits. This enables asynchronous transfer between circuits duplicated in the asynchronous clock domains.

Systems, methods, and apparatuses for fault tolerance and detection are described. For example, an apparatus including circuitry to replicate input sources of an instruction; arithmetic logic unit (ALU) circuitry to execute the instruction with replicated input sources using single instruction, multiple data (SIMD) hardware to produce a packed data result; and comparison circuitry coupled to the ALU circuitry to evaluate the packed data result and output a singular data result into a destination of the instruction is described.

A management system for a plant facility is disclosed. The system includes a first field device that measures a process value, a first control node that calculates a first control value based on the process value, a second field device that operates according to the first control value, and an application node that configures one or more parameters for calculating the first control value. The first control node compares the first control value with a second control value calculated by one of the first field device, a second control node, and the application node. When determining that the first and the second control value are identical, the first control node sets the first control value to the second field device.

A management system for a plant facility is disclosed. The system includes a first field device that measures a process value, a first control node that calculates a first control value based on the process value, a second field device that operates according to the first control value, and an application node that configures one or more parameters for calculating the first control value. The first control node compares the first control value with a second control value calculated by one of the first field device, a second control node, and the application node. When determining that the first and the second control value are identical, the first control node sets the first control value to the second field device.

A safety thread scheduler configured to schedule a check thread for a critical thread being run on one of a plurality of execution units, the check thread being a duplicate of the critical thread, wherein the safety thread scheduler is configured to schedule the check thread to begin being run on a second one of the plurality of execution units before the end of a safety time-window for scheduling the check thread. The safety thread scheduler is further configured to allow the check thread, when the check thread is running on the second one of the plurality of execution units, to be interrupted by a further thread and to re-schedule the check thread to be resumed by expiry of a re-scheduling time limit.

A processing system includes safety thread scheduling circuitry which schedules a check thread, being a duplicate of a critical thread, to be executed on a second of a plurality of parallel execution units other than a first execution unit upon which the critical thread is run. The processor further includes comparison circuitry which will compare a result of the critical thread with a result of the check thread, and raise error signal if the results do not match. The safety thread scheduling circuitry is configured to detect when one of the execution units is idle, and if none of the execution units is detected to be idle by the expiry of a safety time-window, to interrupt a non-critical thread executing on a non-idle one of the execution units and select the non-idle execution unit as the second execution unit to execute the check thread in place of the interrupted thread.

An abnormality determination means performs detection of abnormality of one of the pairs of detection means at a normal speed, and performs detection of abnormality of the other of the pairs at a speed not higher than the normal speed, and, when a sign of abnormality of the detection means is detected at the normal speed, a CPU performs switching to the other normal pair and continues control, and the abnormality determination means performs detection of abnormality of the other normal pair at the normal speed, and meanwhile, continues to perform detection of abnormality of the abnormal pair at a speed not higher than the normal speed.