Patent classifications
G06F11/1658
Interface for memory readout from a memory component in the event of fault
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.
Error recovery method and apparatus
An error recovery method and apparatus, and a system are disclosed. At least two CPUs in a lockstep mode can exit the lockstep mode when an error occurs in at least one CPU, and the CPU in which the error occurs and a type of the error are determined. When the error can be recovered, the CPU in which the error occurs can be recovered according to a correctly running CPU. This helps the at least two CPUs run again at a position at which a service program is interrupted.
Memory device for efficiently determining whether to perform re-training operation and memory system including the same
A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.
METHOD FOR MANAGING HOST MEMORY BUFFER, MEMORY STORAGE APPARATUS, AND MEMORY CONTROL CIRCUIT UNIT
A method for managing a host memory buffer, a memory storage apparatus, and a memory control circuit unit are provided. The method includes: detecting whether a system abnormality occurs; copying a first command and first data corresponding to the first command stored in a data buffer of a host system to the memory storage apparatus in response to determining that the system abnormality occurs; executing an initial operation after copying the first command and the first data, wherein the initial operation initializes a part of a hardware circuit in the memory storage apparatus and does not initialize another part of the hardware circuit in the memory storage apparatus; and re-executing the first command stored in the memory storage apparatus after initializing the part of the hardware circuit.
Programming memory cells with concurrent redundant storage of data for power loss protection
Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.
MEMORY DEVICE FOR EFFICIENTLY DETERMINING WHETHER TO PERFORM RE-TRAINING OPERATION AND MEMORY SYSTEM INCLUDING THE SAME
A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.
BACKUP IMAGE RESTORE
An example apparatus includes a virtual drive controller module to receive a read request from a guest virtual machine (VM) during a restore operation. The apparatus also includes a virtual drive manager module to determine whether data associated with the read request is stored in a storage volume of the guest VM using a sector mapping lookup table during the restore operation. In response to a determination that the data is absent in the storage volume, the virtual drive manager module is to copy the data from a backup image associated with the guest VM to the storage volume, update the sector mapping lookup table to indicate that the data is stored in the storage volume, and transmit the data to the guest VM.
SCALING QUORUM BASED REPLICATION SYSTEMS
A computer determines whether it has received user input or a node within a replica set has reached a capacity threshold. Based on receiving user input or determining that a node within a replica set has reached a capacity threshold, creating a snapshot of the data stored in the replica set and partitioning the data based on the created snapshot. The computer then initializing nodes within a new replica set and moves a partition from the original replica set to the new replica set before deleting the other partition from the old replica set.
Method of recovering application data from a memory of a failed node
A method of recovering application data from the memory of a failed node in a computer system comprising a plurality of nodes connected by an interconnect and of writing the application data to a replacement node; wherein a node of the computer system executes an application which creates application data storing the most recent state of the application in a node memory; the node fails; the node memory of the failed node is then controlled using a failover memory controller; and the failover memory controller copies the application data from the node memory of the failed node to a node memory of the replacement node over the interconnect.
Method of Site Isolation Protection, Electronic Device and System Using the Same Method
A method of site isolation protection includes the following steps. A set of clustered engines including a first engine at a first site and a second engine at a second site is provided. A Fiber Channel (FC) connection and an Ethernet connection between the first and the second sites are provided. Whether an Ethernet Heartbeat (EH) from one of the first engine and the second engine through the Ethernet connection exists is detected when the FC connection fails. One of the first engine and the second engine is shut down when the EH exists. Furthermore, a quorum service at a client site is provided in different IP domain to further protect site isolation from happening, while the FC connection and Ethernet Heartbeat connection failed at the same time.