Technologies for ensuring functional safety of an electronic device include receiving data by a primary and secondary hardware unit and performing a function on the data. Each of the primary and secondary hardware unit perform the same function on their respective set of data to generate corresponding results. A determination is made whether the hardware units are synchronized and the results can be compared. If so, the results are compared and an alert is generated if the results do not match.

An apparatus has two or more processing elements to redundantly process a same processing workload; and divergence detection circuitry to detect divergence between the plurality of processing elements. When a correctable error is detected by error detection circuitry of an erroneous processing element, the erroneous processing element signals detection of the correctable error to another processing element, to control the other processing element to delay processing to maintain a predetermined time offset between the erroneous processing element and the other processing element.

A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.

An apparatus has two or more processing elements to redundantly process a same processing workload; and divergence detection circuitry to detect divergence between the plurality of processing elements. When a correctable error is detected by error detection circuitry of an erroneous processing element, the erroneous processing element signals detection of the correctable error to another processing element, to control the other processing element to delay processing to maintain a predetermined time offset between the erroneous processing element and the other processing element.

The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types of communication delays inherent in explicit synchronization. By globally deploying a number of time masters that are based on various types of time references, the time masters may serve as primary time references. Through an interactive interface, the techniques may track, calculate and record data relative to each time master thus providing the distributed systems with causal timestamps.

Systems and methods include receiving, values of one or more first external time variables from a first external node and values of one or more second external time variables from a second external node. The values of one or more local time variables of the local node are adjusted based at least upon the values of the one or more first external time variables and the values of the one or more second external time variables.

A multi-core processor connected to main memory or peripheral device and having dual modular redundancy mode in which each processor performs the same task includes a first processor which generates first write-in data by performing the task, and writes the first write-in data to the main memory or peripheral device after fault detection operation on the first write-in data, a second processor which generates second write-in data by performing the task, and prevents writing of the second write-in data to the main memory or peripheral device after the fault detection operation on the second write-in data, and a fault manager which performs the fault detection operation by comparing the first write-in data with the second write-in data in the mode, wherein the first write-in data is written to the main memory using first data cache, which is managed using dirty bit indicating whether to synchronize with the main memory.

There is provided a technique of time delivery in a computing system comprising a system call interface (SCI) located in a kernel space and operatively connected to a time client located in a user space. The technique comprises: using a time agent component located in the user space to measure data indicative of delay in a system time delivery and to derive therefrom a system time delivery error TE.sub.S2C; using TE.sub.S2C to enable correction of system time; and sending by the SCI the corrected system time in response to a Read Clock RT (RCRT) call received from the time client. The method can further comprise: measuring data indicative of delays in the system time delivery for RCRT calls with different priorities; and in response to a system time request received from the time client, providing the time client with system time corrected per TE.sub.S2C corresponding to the recognized priority thereof.

A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.

A method for managing communications involving a lockstep processing comprising at least a first processor and a second processor can include receiving, at a data synchronizer, a first signal from a first device. The method can also include receiving, at the data synchronizer, a second signal from a second device. In addition, the method can include determining, by the data synchronizer, whether the first signal is equal to the second signal. When the first signal is equal to the second signal, the method can include transmitting, by the data synchronizer, the first signal to the first processor and the second signal to the second processor. Specifically, in example embodiments, transmitting the first signal to the first processor can occur synchronously with transmitting the second signal to the second processor.