A system, method, and auditing device for processing electronic devices to detect CPI. The auditing device may include a user interface for communicating information and receiving user input. The auditing device may also include a number of interfaces operable to communicate with the one or more electronic devices. The auditing device may also include a memory operable to store a plurality of libraries providing information for detecting CPI on a number of electronic devices including a number of makes, models, and configurations. The auditing device may also include logic operable to utilize the plurality of libraries to detect CPI included on the one or more electronic devices communicating with the testing device, record an identification of an electronic device in response to detecting the CPI is present on the electronic device, and store an alert associated with the identification indicating that CPI is present on the electronic device.

A multi-core processor connected to main memory or peripheral device and having dual modular redundancy mode in which each processor performs the same task includes a first processor which generates first write-in data by performing the task, and writes the first write-in data to the main memory or peripheral device after fault detection operation on the first write-in data, a second processor which generates second write-in data by performing the task, and prevents writing of the second write-in data to the main memory or peripheral device after the fault detection operation on the second write-in data, and a fault manager which performs the fault detection operation by comparing the first write-in data with the second write-in data in the mode, wherein the first write-in data is written to the main memory using first data cache, which is managed using dirty bit indicating whether to synchronize with the main memory.

Techniques are provided for performing automated operations to enable first-failure data capture functionality during initialization of multiple lockstep processors. Following a hardware reset of two lockstep processors, an indication is received of one or more crosscheck errors regarding the operation of the two lockstep processors. In response to the crosscheck errors, crosscheck first-failure data capture (FFDC) data is saved to one or more memory areas that are persistent across a hardware reset, and it is determined whether a predefined reset threshold has been satisfied. Responsive to determining that the predefined reset threshold has been satisfied, the crosscheck FFDC data from the one or more persistent memory areas is analyzed and one or more crosscheck initialization codes are responsively generated. An additional hardware reset is initiated.

This disclosure provides an automation controller method, system and apparatus including a redundant watchdog utilizing a safety partner controller. According to an exemplary controller, the controller includes a first processing unit, a second processing unit, and an integrated circuit configured to receive as inputs fault indicator signals from the first and second processing units, and the integrated circuit configured to disable I/O communications for a fault condition detected by the first or second processing units.

Systems and methods include receiving, values of one or more first external time variables from a first external node and values of one or more second external time variables from a second external node. The values of one or more local time variables of the local node are adjusted based at least upon the values of the one or more first external time variables and the values of the one or more second external time variables.

A computer system includes a plurality of computer nodes, each including an external communications unit. An application unit executes processing in accordance with a processing request. A synchronization unit establishes synchronization of the processing between each computer node and other computer nodes. The processing is executed by each computer node, and an inter-node communications unit executes transmission/reception of information between each computer node and the other computer nodes. The synchronization unit transmits the processing request to the other computer nodes via the inter-node communications unit, the processing request being received by the external communications unit. Also, the synchronization unit receives processing requests from the other computer nodes as well via the inter-node communications unit. Based on the number of the computer nodes that have received the same processing request via the external communications units, the synchronization unit selects a processing request that should be executed by the application unit.

A system and method that detects hardware and software errors in an embedded system that includes detecting or measuring an operating state; causing one or more computation engines to operates in group synchrony; causing one or more active monitors that monitor the computation engines to an automotive integrity level to operate in group synchrony; synchronizing the communication between and from the plurality of computation engines and the plurality of active monitors, respectively; and arbitrating the output generated by the computation engines and the active monitors.

Techniques are provided for performing automated operations to enable first-failure data capture functionality during initialization of multiple lockstep processors. Following a hardware reset of two lockstep processors, an indication is received of one or more crosscheck errors regarding the operation of the two lockstep processors. In response to the crosscheck errors, crosscheck first-failure data capture (FFDC) data is saved to one or more memory areas that are persistent across a hardware reset, and it is determined whether a predefined reset threshold has been satisfied. Responsive to determining that the predefined reset threshold has been satisfied, the crosscheck FFDC data from the one or more persistent memory areas is analyzed and one or more crosscheck initialization codes are responsively generated. An additional hardware reset is initiated.

A system, method, and auditing device for processing electronic devices to detect CPI. The auditing device may include a user interface for communicating information and receiving user input. The auditing device may also include a number of interfaces operable to communicate with the one or more electronic devices. The auditing device may also include a memory operable to store a plurality of libraries providing information for detecting CPI on a number of electronic devices including a number of makes, models, and configurations. The auditing device may also include logic operable to utilize the plurality of libraries to detect CPI included on the one or more electronic devices communicating with the testing device, record an identification of an electronic device in response to detecting the CPI is present on the electronic device, and store an alert associated with the identification indicating that CPI is present on the electronic device.

The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types of communication delays inherent in explicit synchronization. By globally deploying a number of time masters that are based on various types of time references, the time masters may serve as primary time references. Through an interactive interface, the techniques may track, calculate and record data relative to each time master thus providing the distributed systems with causal timestamps.