A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.

A method for synchronizing processor units. An external synchronizer is communicated with to determine whether an undesired amount of skew is present between a first processor unit and a second processor unit in communication with a synchronization system. The first processor unit is selectively directed to perform an action without generating a needed result such that the undesired amount of skew between the first processor unit and the second processor unit is reduced when the undesired amount of skew is present in the first processor unit. The first processor unit and the second processor unit are associated with each other for a high integrity mode in which integrity checks are performed on corresponding messages generated by the first processor unit and the second processor unit.

Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.

A system and method enables loosely-coupled lock-step computing including sensors that detect or measure a physical property and server groups. Each server group is serially linked to another server group and includes server instances operating in virtual synchrony. Virtual synchrony middleware receives outputs from multiple server instances and renders a single reply based on the outputs from the multiple server instances. The virtual synchrony middleware replicates and orders incoming requests to the server groups to ensure each of the server instances of that server group receives the same incoming requests in the same order.

An exemplary fault-tolerant computing system comprises a secondary processor configured to execute in delayed lock step with a primary processor from a common program store, comparators in the store data and writeback paths to detect a fault based on comparing primary and secondary processor states, and a writeback path delay permitting aborting execution when a fault is detected, before writeback of invalid data. The secondary processor execution and the primary processor store data and writeback may be delayed a predetermined number of cycles, permitting fault detection before writing invalid data. Store data and writeback paths may include triple module redundancy configured to pass only majority data through the store data and writeback path delay stages. Some implementations may forward data from the store data path delay stages to the writeback stage or memory if the load data address matches the address of data in a store data path delay stage.

A computing apparatus includes a transaction-record memory and a comparator. The transaction-record memory is to receive and store one or more sequences of transaction records, each transaction record including a unique transaction ID and a transaction payload. The comparator is to compare the payloads of transaction records having the same transaction ID, and to initiate a responsive action in response to a discrepancy between the compared transaction payloads.

A system for diagnosing a register of a lockstep module of a slow clock domain, includes a functional intellectual property (IP) core and a lockstep IP core configured to work in the slow clock domain, a fast bus module configured to read a value of a register of the functional IP core and a value of a register of the lockstep IP core, and record a state change of the register of the functional IP core, and a central processing unit (CPU) configured to determine whether the register of the functional IP core and the register of the lockstep IP core are normal according to the value of the register of the functional IP core, the value of the register of the lockstep IP core, and the state change of the register of the functional IP core.

A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.

A process control system is provided which has at least one OPC client and one OPC server which communicate via a standardized OPC interface. Furthermore the process control system has at least two redundantly operated control devices which each communicate with the OPC server by means of a coupling device. Each control device is designed to provide process variables and status information. The status information contains the current role of the respective control device, wherein the current role is either that of a main control device or an auxiliary control device. The OPC server is designed to detect the main control device in response to the status information of at least one control device, to register a list of variables generated by the OPC client at the main control device and/or to transmit to the OPC client only the process variables which have been provided by the main control device.

Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnosed result.