A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects

A method includes: causing at least three processors to perform a same process; extracting, when one of the at least three processors outputs different operational information generated by performing the same process, majority processors with which outputted operational information are the same and a minority processor with which different operational information is outputted; and controlling one of the two redundant processors to output a result of the same process.

This disclosure provides an automation controller method, system and apparatus including a redundant watchdog utilizing a safety partner controller. According to an exemplary controller, the controller includes a first processing unit, a second processing unit, and an integrated circuit configured to receive as inputs fault indicator signals from the first and second processing units, and the integrated circuit configured to disable I/O communications for a fault condition detected by the first or second processing units.

A circuit includes primary register circuitry to receive a first signal to write a first value to the primary register circuitry; secondary register circuitry to receive a second signal to write a second value to the secondary register circuitry; a counter configured to count a set amount of time from when the first signal is received; and a controller coupled to the counter. The controller receives at least one of: a third signal indicating whether the second signal was detected within the set amount of time, and a fourth signal indicating whether the first value is the same as the second value.

Camera heads and associated systems, methods, and devices for inspecting and/or mapping pipes or cavities are disclosed. A camera head may be coupled to a push-cable and may include one or more image sensors to capture images and/or videos from interior of the pipe or cavity. One or more multi-axis sensors may be disposed in the camera head to sense data corresponding to movement of the camera head within the pipe or cavity. The images and/or videos captured by the image sensors may be used in conjunction with the data sensed by the multi-axis sensors to generate information pertaining to the pipe or cavity may be generated.

Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core 11 and the second CPU core 12 respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.

This disclosure provides an automation controller method, system and apparatus including a redundant watchdog utilizing a safety partner controller. According to an exemplary controller, the controller includes a first processing unit, a second processing unit, and an integrated circuit configured to receive as inputs fault indicator signals from the first and second processing units, and the integrated circuit configured to disable I/O communications for a fault condition detected by the first or second processing units.

A nuclear power plant control system including: a detection unit for detecting a specific event occurring in the nuclear power plant; an on-site equipment handling the event; and a majority decision judging device and an on-site equipment control device which constitute a plurality of control devices respectively operating independently. Each of the control devices includes a plurality of arithmetic units which perform arithmetic processes independently and in parallel based on a detection result of the detection unit, and output a signal for controlling the on-site equipment according to the results of operations of the arithmetic processes. The plurality of arithmetic units perform a matching process for harmonizing process statuses of the arithmetic processes of respective arithmetic units with each other when starting up the control devices, and after completing the matching process, respectively perform the arithmetic processes independently and in parallel.

A data processing network is for performing a plurality of successive data processing steps in a redundant and validated manner. The data processing steps are each used to generate output data from input data. At least some output data from a first data processing step are at the same time input data of a further data processing step. At least a first data processing module and a second data processing module are provided for performing each data processing step. The data processing network includes a comparator module. The first data processing module and the second data processing module are configured to perform the data processing steps, optionally in a first working mode with parallel operation, or in a second working mode with an upstream data processing module and a downstream data processing module.

A technique for enhancing reliability is provided. A semiconductor device includes a main device which operates in a delayed lockstep mode, a sub device which operates in parallel to the main device in a delayed lockstep mode, a delay circuit which delays an output of the main device, a switching circuit which switches the main device to the sub device according to failure information of the main device.