This disclosure provides an automation controller method, system and apparatus including a redundant watchdog utilizing a safety partner controller. According to an exemplary controller, the controller includes a first processing unit, a second processing unit, and an integrated circuit configured to receive as inputs fault indicator signals from the first and second processing units, and the integrated circuit configured to disable I/O communications for a fault condition detected by the first or second processing units.

Exemplary embodiments of the present invention relate to a failure recovery apparatus of digital logic circuit and method thereof when a fault occurs in the digital logic circuit. A failure recovery apparatus according to an embodiment of the present invention comprises: a fault detection block configured to determine fault occurrence by comparing output results of a plurality of digital logic circuit which perform the same operation using a clock having a first cycle; and a failure recovery block configured to perform a failure recovery operation of the plurality of digital logic circuit by using a clock having a second cycle which is longer than the first cycle when it is determined as that a fault occurs. According to exemplary embodiments of the present invention, when a fault occurs in digital logic circuits due to external factors, it provides high reliability in failure recovery of the digital logic circuits.

A computing system includes at least a first division and a second division. The first division has a first clock rate and the second division has a second clock rate. The computing system includes a first processor configured to execute a task on the first division and a second processor configured to execute the task of the second division. The task executed on the first division operates according to the first clock rate, and the task executed on the second division operates according to the second clock rate. A method of executing a task in order to reduce common mode failures in a computing system includes varying a program speed of each of the plurality of divisions such that the task, when executed on a corresponding one of the plurality of divisions, operates at a clock rate according to the corresponding one of the plurality of divisions.

A data processing network is for performing a plurality of successive data processing steps in a redundant and validated manner. The data processing steps are each used to generate output data from input data. At least some output data from a first data processing step are at the same time input data of a further data processing step. At least a first data processing module and a second data processing module are provided for performing each data processing step. The data processing network includes a comparator module. The first data processing module and the second data processing module are configured to perform the data processing steps, optionally in a first working mode with parallel operation, or in a second working mode with an upstream data processing module and a downstream data processing module.