G06F11/18

ARCHITECTURE AND APPARATUS FOR ADVANCED ARBITRATION IN EMBEDDED CONTROLS
20170277604 · 2017-09-28 ·

A method of arbitrating conflicting outputs in a redundant control system. Execution data of a task executed by each controller in the redundant control system is recorded. The execution data includes an initial timestamp of each execution stream, identification of critical functions in each execution stream, and parameter values used by the critical functions. A path executed by each controller is identified based only on the critical functions executed for each execution stream. The recorded execution data of each executed path is applied to an arbitration module. An output result from one of the respective controllers selecting, by an arbitration module, based on the recorded execution data of each executed path. The output result of the selected controller is communicated to a next module for further processing.

Device and system including adaptive repair circuit

A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.

Device and system including adaptive repair circuit

A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.

Microcontroller utilizing redundant address decoders and electronic control device using the same

The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part.

Method and system for managing interconnection of virtual network functions

A method and apparatus is disclosed herein for use of a connectivity manager and a network infrastructure including the same. In one embodiment, the network infrastructure comprises one or more physical devices communicably coupled into a physical network infrastructure or via the overlay provided by the physical servers; and a virtual network domain containing a virtual network infrastructure executing on the physical network infrastructure. In one embodiment, the virtual network domain comprises one or more virtual network functions connected together through one or more links and executing on the one or more physical devices, and one or more interfaces coupled to one or more network functions via one or more links to communicate data between the virtual network domain and at least one of the one or more physical devices of the physical network infrastructure while the virtual network domain is isolated from other virtual infrastructures executing on the physical network infrastructure.

Facilitating practical byzantine fault tolerance blockchain consensus and node synchronization
11397725 · 2022-07-26 · ·

Implementations of the present disclosure include setting, by a first consensus node, a timer that runs out before a timeout of a view change; sending, to a second consensus node, a request for one or more consensus messages missing by the first consensus node in response to the timer running out; receiving, from the second consensus node, the one or more consensus messages each digitally signed by a private key of a corresponding consensus node that generates the respective one or more consensus messages; and determining that a block of transactions is valid, if a quantity of commit messages included in the received one or more consensus messages is greater than or equal to 2f+1, where f is a maximum number of faulty nodes that is tolerable by the blockchain based on practical Byzantine fault tolerance.

APPARATUSES AND METHODS FOR WRITING DATA TO A MEMORY
20210406208 · 2021-12-30 · ·

Apparatuses and methods for writing data to a memory array are disclosed. When data is duplicative across multiple data lines, data may be transferred across a single line of a bus rather than driving the duplicative data across all of the data lines. The data from the single data line may be provided to the write amplifiers of the additional data lines to provide the data from all of the data lines to be written to the memory. In some examples, error correction may be performed on data from the single data line rather than all of the data lines.

APPARATUSES AND METHODS FOR WRITING DATA TO A MEMORY
20210406208 · 2021-12-30 · ·

Apparatuses and methods for writing data to a memory array are disclosed. When data is duplicative across multiple data lines, data may be transferred across a single line of a bus rather than driving the duplicative data across all of the data lines. The data from the single data line may be provided to the write amplifiers of the additional data lines to provide the data from all of the data lines to be written to the memory. In some examples, error correction may be performed on data from the single data line rather than all of the data lines.

Consensus-forming method in network, and node for configuring network
11212165 · 2021-12-28 · ·

A consensus building method suitable when f Byzantine failure nodes (f is an integer equal to or larger than 1 and smaller than N/3) are assumed in a network having N nodes (N is an integer equal to or larger than 1) participating in consensus building, comprising the steps of: receiving a first message from other node which communicates that the other node determined a message including data subject to consensus building valid as a proposal, when the number of received first messages reach a predetermined value Q, transmitting a second message to each node which communicates that it is accepting the proposal, and when the number of received first messages do not reach the predetermined value Q, transmitting a third message to each node which communicates that it is dismissing the proposal, when the number of received second messages reach a predetermined value Q, transmitting a fourth message to each note which communicates that it is treating the proposal as agreed in the network, and when the number of received third messages reach a predetermined value Q, transmitting a fifth message for proceeding to a next round (a unit of consensus building process is called “round”.) to each node, wherein the predetermined value Q is an integer equal to or larger than (f+N+1)/2 when a value of f is known, and wherein when the number of received first message reaches a predetermined value Q, a lock is set to limit behaviors thereafter.

Two die system on chip (SoC) for providing hardware fault tolerance (HFT) for a paired SoC

Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.