A method for performing dataload protocol operation testing in an avionics Line Replaceable UNIT (LRU) is disclosed. In some embodiments, the method includes sending a request to initiate transfer of a dataload sequence from an external data loader to a target hardware. The method further includes receiving an acceptance status from the target hardware to initiate transfer of the dataload sequence based on at least one of the valid or invalid dataload sequence request or response. The method further includes determining, based on the invalid dataload sequence request or response, occurrence of one or more failure scenarios associated with at least one of: the transmission of the dataload sequence; and the receiving of the acceptance status from the target hardware on different stages of dataload operation.

A modular system is described which can provide high frequency monitoring of power use and responsive control as well as enabling network connectivity for centralised monitoring and operation. One modular system consists of a communications bus, end caps, and a combination of the modules providing communications, power metering, relay control and battery backup. Each modular system can be configured with a combination of modular units as needed for the application. A combination of bus communication monitoring and tilt detection provides security against external tampering after installation.

A method for processing data between host computer and CPLD provides a host computer, a circuit board comprising a UART unit, a pre-debugged hardware, and a CPLD. The UART unit communicates with the host computer via UART. The method further provides the CPLD coupled between the UART unit and the pre-debugged hardware and allows the CPLD to receive data from the host computer via the UART unit and to analyze the data. According to the method, the CPLD debugs the pre-debugged hardware according to the analyzed data and obtains a result of debugging. The CPLD outputs the result and allows the CPLD to transmit the result to the host computer via the UART unit. A system using the method is also provided.

A method for testing peripheral component interconnect express (PCIe) devices is provided. The method implemented at a PCIe testing system detects that one or more PCIe devices have been inserted into one or more PCIe buses of a data processing system. In response to the detection, the PCIe testing system scans all PCIe buses of the data processing system to discover the one or more PCIe devices. For each of the PCIe devices discovered, the PCIe testing system repairs and retrains a PCIe link associated with the PCIe device, without rebooting the data processing system. The PCIe testing system loads a device driver instance for the PCIe device to be hosted by an operating system. The PCIe testing system then executes a test routine to concurrently test the one or more PCIe devices via the respective device driver instances.

In a Peripheral Component Interconnect Express (PCIe) system, a first PCIe apparatus determines that at least one of lanes of a link between the first PCIe apparatus and a second PCIe apparatus is disabled, wherein the link includes M lanes numbered in a first order. Based upon the determination, the first PCIe apparatus obtains a number N indicating a number of available lanes of the link by performing a lane negotiation with the second PCIe apparatus. Then, a processor determines that N<M/2. Based upon the determination, the first PCIe apparatus re-numbers at least some of the lanes of the link in a reverse order opposite to the first order as instructed by the processor. At last, the first PCIe apparatus continue to perform a negotiation with the second PCIe apparatus to obtain available lanes.

Using a framing protocol, an application specific integrated circuit (ASIC) in an emulation system may transmit a start-of-packet molecule to a serializer-deserializer (SerDes) interface of a switching ASIC in a gap cycle leading up to an emulation cycle such that the switching ASIC may start routing mission data through the SerDes interface during the emulation cycle. The ASIC may transmit an end-of-packet molecule at a first gap cycle to the SerDes interface of the switching ASIC such that the switching ASIC may stop routing data through the SerDes interface during the gap cycles. The start-of-packet molecule may include a start-of-packet word, a status word, cyclic redundancy check word, and an idle word. The end-of-packet molecule may include an end-of-packet word, a status word, a cyclic redundancy check word, and an idle word.

A system for monitoring of integrity of a communication bus includes a communication bus cooperating with at least one transmitter configured to generate and transmit a signal on communication bus. At least one receiver is configured to receive a signal generated by the transmitter and transmitted on communication bus. The receiver is further configured to receive the transmitted signal as well as any reflected signals arising from non-impedance matched section in communication bus and wherein a time difference between transmitted pulse width and received pulse width indicates a distance between the non-impedance matched section and the transmitter on the communication bus.

A method for error management in bus communication is disclosed. A first bus subscriber generates a first bus message and writes a bus error code into a bus data area of a first bus message. The second bus subscriber identifies the error by evaluating the bus error code. The first bus subscriber stores an error identification of the error, generates a first bus message and writes the bus error code into the bus data area of the first bus message. A second bus message with a request for transmission of the error identification is generated by the second bus subscriber. A third bus message is generated by the first bus subscriber and the stored error identification is written into the bus data area of the third bus message. The second bus subscriber identifies the errors by evaluating the bus error code and the error identification.

A method for determining fault types in a circuit design includes obtaining circuit elements, a first observation point of a first circuit element, and a first diagnostic point of a first safety circuit device. The method further includes determining a first cone of influence including a first subset of the circuit elements based on the first observation point. The first subset of the circuit elements includes the first circuit element. Further, the method includes determining a first safety cone including a second subset of the circuit elements based on the first diagnostic point. The first safety cone includes the first safety circuit device. The method further includes determining a fault type associated with the circuit elements based on an intersection between the first cone of influence and the first safety cone.

A method for connecting an input/output interface of a testing device equipped for testing a control unit to a model of a technical system present in the testing device. The interface connects the control unit to be tested or connects a technical system to be controlled; the model to be connected to the input/output interface is a model of the technical system to be controlled or a model of the control unit to be tested. The testing device has a plurality of input/output functions connected to the model and provides an interface hierarchy structure and a function hierarchy structure. The method has an automatic configuration of compatible connections between the interface hierarchy structure and the function hierarchy structure so that the model present in the testing device communicates through the compatible connections with the control unit to be tested or the technical system to be controlled.