A computing system can comprise a processing resource and a memory device coupled together via a first transmission link. The processing resource can be configured to test the first transmission link in response to the memory device failing to execute a command by sending the command to the memory device again for retry and monitoring the first transmission link for signals that indicate whether the command was executed by the memory device.

A debugging device includes a plurality of debug units, a UART port, and a processor. The debugging device is communicated with an electronic device through the UART port. The processor can receive debug signals from the terminal through the UART port, generate a plurality of debug controlling commands based on the debug signals, and send the plurality of debug controlling commands to the plurality of debug units, for controlling the plurality of debug units to debug the electronic device according to the plurality of debug controlling commands.

A system includes a battery and a monitoring circuit coupled to the battery. The monitoring circuit includes a sense circuit and a peripheral device coupled to the sense circuit. The peripheral device includes a universal asynchronous receiver-transmitter (UART) receiver having an adaptive sample timing circuit with a numerically-controlled oscillator (NCO) circuit. The peripheral device also includes memory coupled to the UART receiver and configured to store battery monitoring data.

A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.

This application discloses an automatic switching system and method for a front end processor (FEP). The system includes: at least one external device and a FEP assembly. The FEP assembly is connected to the at least one external device. The FEP assembly provides services upward by using a primary memory, a primary TO manager, a secondary memory, and a secondary TO manager, and is connected downward to the at least one external device by using at least one primary driver and at least one secondary driver. The FEP assembly is configured to use the at least one secondary driver as a new primary driver when there is a fault in a communication link between the at least one primary driver and the at least one external device, to transmit a control instruction to the at least one external device and acquire data from the at least one external device.

Methods, systems, and computer readable media for smart network interface card testing are disclosed. One example method occurs at a network interface card (NIC) comprising a network processing unit executing a monitoring agent for monitoring data traversing the NIC. The method includes obtaining, from a test system or a test traffic generator, at least one test packet; generating, using the monitoring agent, NIC processing information associated with processing the at least one test packet, wherein generating the NIC processing information includes monitoring application layer events, presentation layer events, session layer events, transport layer events, network layer events, driver layer events, kernel layer events, or other events involving the NIC and generating the NIC processing information using the monitored events; and storing or providing the NIC processing information for data analysis.

An apparatus is for testing a device to be supplied with power via USB Power Delivery (USB-PD). The apparatus includes at least one USB Type-C connector configured to be connected to the device to be supplied with power to be tested, the at least one USB Type-C connector including a power supply terminal. Processing circuitry of the apparatus is configured to verify that a voltage at the power supply terminal is lower than a first threshold, verify a role of the device, generate requests representative of power supply configurations supported by the role of the device, and verify compatibility of the power supply configurations supported by the device with standardized power supply configurations.

A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

An apparatus to initialize a port includes a first input-output port to connect to a first device and a control unit to initialize all input-output ports of the apparatus when the apparatus is booted and to skip a power-on self-test (POST) of the first input-output port in response to a request to skip initialization of the first input-output port while the first input-output port is enabled.

According to various embodiments, there is provided a method for testing a device driver software of a processor, the method including: configuring an identity field of a testing device based on a device emulation command received through a first testing device interface, wherein the identity field is accessible by the device driver software for recognising the testing device; running an emulation program on the testing device, the emulation program including an emulation of a human input device in accordance with the configured identity field; receiving an input instruction in the testing device via the first testing device interface, the input instruction indicative of an input performable on the emulated human input device; the emulation program, emulating an output signal generatable by the emulated human input device in response to the input being performed on the emulated human input device; outputting the emulated output signal via a second testing device interface to the device driver software of the processor to translate the emulated output signal to an event in an application program running on the processor.