Trap sub-portions of computer-readable instructions and related systems, methods, and devices are disclosed. A processing circuit includes a processing core including a program counter to cycle through addresses and a data storage device including computer-readable instructions stored thereon. Sub-portions of the computer-readable correspond to subroutines. Locations of the sub-portions within the data storage device are associated with the addresses. A first sub-portion at a first location within the data storage device is indicated by a first address. First trap sub-portions at first trap locations are indicated by first trap addresses. The first trap addresses are different from the first address by only a single bit. The first trap sub-portions instruct the processing core to execute first trap subroutines to jump to the first address or back to themselves.

A method for identifying electronic device is applied to a terminal device and includes: sending, in response to receiving a power-on signal of the electronic device, a detection signal to the electronic device; acquiring waveform information of the detection signal; and determining a type of the electronic device according to the waveform information.

An on-chip debugging device and method is provided. The on-chip debugging device includes: an external interface module configured for outputting chip debugging state information to an external debugger and receiving a control instruction of the external debugger; a debugging mode control module configured for setting a to-be-sampled type of a specified chip internal signal and setting a debugging trigger condition according to the debugging configuration of the external debugger or the internal CPU; a debugging monitor module configured for sampling and recording the internal signal of the chip of the specified type so as to identify the running state of the chip; and a debugging information processing module configured for storing the running state of the chip in an internal debugging memory and sending it to the external debugger by the external interface module or sending it to the internal CPU via an internal bus. The on-chip debugging functions which are relatively simple, occupy less resources and have more powerful functions can be realized by the device and the method.

A first server of a storage controller is configured to communicate with a host via a first bus interface, and a second server of the storage controller is configured to communicate with the host via a second bus interface. Data is written from the host via the first bus interface to a cache of the first server and via the second bus interface to a non-volatile storage of the second server. The data stored in the cache of the first server is periodically compared to the data stored in the non-volatile storage of the second server.

A computer system and a debugging method thereof are provided. The computer system includes a circuit board, a memory, a circuit board image, and a processor. The circuit board includes a plurality of connection interfaces configured to be electrically coupled to a plurality of hardware devices. The memory stores a basic input/output system program. The basic input/output system program includes a power-on self-test program. The processor loads the basic input/output system program to perform a boot process when the computer system is powered on, reads and executes the power-on self-test program to detect the hardware devices electrically coupled to the connection interfaces, displays the circuit board image on a display, and displays a mark pattern on the circuit board image corresponding to a position of a connection interface image of an abnormal hardware device when the hardware device is detected to be abnormal.

A method and system for detecting faults in a communication interface is disclosed. The communication interface is connected to a field device and a device bus comprising generating periodic diagnostic pulse by a programing unit. The programming unit is communicatively connected to the controller and a controller interface and provides the diagnostic pulse to a multiplexer to periodically apply the diagnostic pulses from the programming unit to a first winding of a transformer. The programming unit provides the diagnostic pulse to the isolation unit. A sensing unit senses a voltage drop across a sense resistor, the sensing unit having an input connected to the sense resistor and an output connected to the programming unit. The sensing unit communicates a sense signal based on the comparison to the programming unit, and switches from a primary or a secondary module to the other based on the sense signal.

Trap sub-portions of computer-readable instructions and related systems, methods, and devices are disclosed. A processing circuit includes a processing core including a program counter to cycle through addresses and a data storage device including computer-readable instructions stored thereon. Sub-portions of the computer-readable correspond to subroutines. Locations of the sub-portions within the data storage device are associated with the addresses. A first sub-portion at a first location within the data storage device is indicated by a first address. First trap sub-portions at first trap locations are indicated by first trap addresses. The first trap addresses are different from the first address by only a single bit. The first trap sub-portions instruct the processing core to execute first trap subroutines to jump to the first address or back to themselves.

Provided are a connector structure, and a skew calculation method and device. Specifically, the connector structure includes: a first Printed Circuit Board (PCB) (12), which includes a first board (122) and a second board (124), and is connected to a testing device; and a second PCB (14), which includes a third board (142) and a fourth board (144), and is connected to the testing device. The first board (122) is connected to the third board (142) through a connector (16).

A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

A portable handheld device receives from a central repository, information on a failed hardware component of a computational device, wherein the information includes an authentication code to permit access to the failed hardware component and a time window in which the failed hardware component is permitted to be accessed. The portable handheld device uses the authentication code to access the failed hardware component for repair or replacement during the time window.