A method of performing a built in test on a watchdog circuit including a watchdog timer includes: initiating the built in test with a processor being monitored by the watchdog circuit, wherein initiating includes enabling a watchdog circuit built in test reset inhibit circuit (WD BIT reset inhibit circuit) connected between an output of an active watchdog integrated reset circuit connected to the processor and a reset input of the processor; and ceasing to provide a strobe signal to the active watchdog integrated reset circuit that resets a watchdog counter in the active watchdog integrated reset circuit, the active watchdog integrated reset circuit causing a reset of the processor via its output when the watchdog counter expires by providing a signal to a reset input of the processor.

In general, according to one embodiment, there is provided a semiconductor integrated circuit including a memory macro. The memory macro includes a first ECC circuit that generates a code corresponding to input data, a memory core including a data storage portion on which reading and writing of data is performed, and an ECC storage portion on which reading and writing of a code is performed, a second ECC circuit that executes, based on data and code read from the memory core, error detection or correction of the data, and circuits that form a path in which data flows to bypass the memory core in a scan test, and form a path in which data flows through each of the data storage portion and the ECC storage portion in a memory test.

A controller comprises an error correction circuit configured to check an error bit number of error bits in the read data and correct the error bits; a read retry range setting circuit configured to reset a preset read retry range with respect to the read data, and set a new read retry range based on the error bit number and an error correction capability of the error correction circuit; a read voltage setting circuit configured to reset the set read voltage and set, as a new read voltage, a voltage among a plurality of voltages of the reset read retry range, corresponding to the new read retry range; and a flash control circuit configured to control the memory device to perform a read retry operation on the stored data, using the new read voltage.

This disclosure concerns a medical device designed for delivering a medical fluid or designed for controlling delivery of a medical fluid, and to a method of operating such a medical device. The medical device comprises a user interface associated with an electronic circuit connected to a first port and to a second port of a controller. The electronic circuit enables the controller to detect actuation of the user interface. The controller is configured to execute the following sequence of steps: first step: configure the first port as an output port and to apply a first signal to the first port; second step: to acquire a second signal from the second port; and third step: to determine on the basis of the second signal if a short circuit has occurred and to generate a short circuit alert signal if applicable.

A computer system is provided that includes a cloud platform that includes a plurality of nodes. Each node includes a processor configured to run virtual machines. The cloud platform includes a fault condition injection engine configured to generate fault conditions on selected nodes of the plurality of nodes. The computer system further includes a user interface system configured to receive user input of fault condition experimentation parameters from a user for a target virtual machine associated with the user. The cloud platform allocates a set of nodes of the plurality of nodes for a controlled sandbox environment configured to run the target virtual machine of the user. The fault condition injection engine generates fault conditions on the allocated set of nodes based on the fault condition experimentation parameters.

Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug information corresponding to the one or more debug communications. Additionally, tunnel logic hardware may be instructed to transfer the debug information from the set of debug registers to one or more test access ports of an intelligent device such as a non-volatile memory storage unit having a microcontroller. In one example, if it is detected that debug permission has been granted during a boot process, a control status register may be unlocked. If, on the other hand, the debug permission is not detected during the boot process, the control status register may be locked. Accordingly, an enable bit of the control status register may be used to activate the tunnel logic hardware only if the control status register is unlocked.

A method for the self-diagnosis of RAM error detection logic of a powertrain controller includes: idling, by a first core, an operation of a second core; testing an error correction code (ECC) module corresponding to a RAM operating by the second core; idling, by the second core, an operation of a core of a plurality of un tested cores; and testing an ECC module corresponding to a RAM operating by the core of the plurality of untested cores.

An error injected error correction code (ECC) word generator generates a set of ECC code words injected with bit errors for being read by an ECC decoder and error reporting hardware. The set of the error injected ECC words has a binomial distribution with regard to a number of the bit errors in a given ECC word of the set. The set of error injected ECC words has a predetermined average ratio of bit errors.

A semiconductor device capable of executing fault injection test on a plurality of failure detection mechanism in a short time is provided. The semiconductor device 1 has a plurality of hierarchical modules and an error control module 100 for controlling errors in the plurality of hierarchical modules. Each hierarchical module has a safety mechanism to detect failures in the functions of the components that make up the hierarchical modules. The error control module 100 includes a status register 120 configured to record data indicative of the status of failure of each hierarchical module, and a fault injection function 110 that outputs an error signal to the status register 120 to perform fault injection test. The error signal is inputted into the safety mechanism via the status register 120.

Embodiments are directed to identifying intermittent faults in a unit under test (UUT), and to mapping interconnections between connection points in a UUT. In one scenario, a testing apparatus includes an interface for electrically attaching the UUT to a testing module and an input circuit for supplying an individual stimulus signal to each unpowered connection point in the UUT. The testing apparatus also includes an active intermittence detecting circuit electronically connected to each connecting point in the UUT. A stimulus signal is applied simultaneously to each connecting line, so that an intermittent fault on any line will generate a trigger on those connection lines that have an intermittent fault. The testing apparatus also includes a logic circuit that determines when a trigger has been generated on the UUT, determines the connection point of the trigger, assigns a timestamp to the intermittent fault, and generates reporting data for the intermittent fault.