An error injected error correction code (ECC) word generator generates a set of ECC code words injected with bit errors for being read by an ECC decoder and error reporting hardware. The set of the error injected ECC words has a binomial distribution with regard to a number of the bit errors in a given ECC word of the set. The set of error injected ECC words has a predetermined average ratio of bit errors.

Embodiments are directed to identifying intermittent faults in a unit under test (UUT), and to mapping interconnections between connection points in a UUT. In one scenario, a testing apparatus includes an interface for electrically attaching the UUT to a testing module and an input circuit for supplying an individual stimulus signal to each unpowered connection point in the UUT. The testing apparatus also includes an active intermittence detecting circuit electronically connected to each connecting point in the UUT. A stimulus signal is applied simultaneously to each connecting line, so that an intermittent fault on any line will generate a trigger on those connection lines that have an intermittent fault. The testing apparatus also includes a logic circuit that determines when a trigger has been generated on the UUT, determines the connection point of the trigger, assigns a timestamp to the intermittent fault, and generates reporting data for the intermittent fault.

Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of testing error-correcting code (ECC) logic. The method includes receiving data for storage in a memory. The method further includes receiving an address indicating a location in the memory to store the data. The method further includes determining if the received address matches at least one of one or more test addresses. The method further includes operating the ECC logic in a normal mode when the received address does not match at least one of the one or more test addresses. The method further includes operating the ECC logic in a test mode when the received address does match at least one of the one or more test addresses.

A compliance user or auditor is enabled to inject failures into a sandbox environment which may be similar to a production service. The sandbox environment, may be monitored by the same automation that watches compliance controls in the production service. As the user injects compliance failures into the sandbox, they may detect the appropriate alerts fire in the monitoring system, thereby gaining trust that the monitoring works as it should. A rich report resulting from the test activities may allow the user or auditor to see how a failure of a compliance control leads to the expected monitoring alert.

A method, apparatus and system for providing a cloud-based disaster recovery test include receiving, at a cloud-based computing platform, a request for a disaster recovery test of at least a portion of a client's data network, in response to the received request, creating an isolated network in the cloud-based computing platform, cloning, in the isolated network, machines and configurations of the at least the portion of the client's data network to be included in the cloud-based disaster recovery test, reserving resources of the cloud-based computing platform based on the cloned machines and configurations of the at least the portion of the client's data network and an associated data handler to be deployed in the cloud-based disaster recovery test, and enabling the cloned machines for use by the client for performing the cloud-based disaster recovery test in the cloud-based computing platform.

A system for detecting false data injection attacks includes one or more sensors configured to each monitor a component and generate signals representing measurement data associated with the component. The system also includes a fault detection computer device configured to: receive the signals representing measurement data from the one or more sensors, receive a fault indication of a fault associated with the component, generate a profile for the component based on the measurement data, and determine an accuracy of the fault indication based upon the generated profile.

An electronic device has a first terminal for receiving power from a connected external device, a second terminal for obtaining information of the external device, and a GND terminal connected to the second terminal. The electronic device causes a resistance between the second terminal and the GND terminal to change, and determines a type of the external device based on a voltage of the first terminal after the resistance is caused to change.

A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.

Aspects disclosed herein relate to periodic non-intrusive diagnosis of lockstep systems. An exemplary method includes comparing execution of a program on a first processing system of the plurality of processing systems and execution of the program on a second processing system of the plurality of processing systems using a first comparator circuit, comparing the execution of the program on the first processing system and the execution of the program on the second processing system using a second comparator circuit, and running a diagnosis program on the second comparator circuit while the comparing using the first comparator circuit is ongoing.

A memory system includes a non-volatile memory unit, a content-addressable memory unit coupled to the non-volatile memory unit, and an error injection logic unit coupled to the non-volatile memory unit and the content addressable memory unit. The non-volatile memory unit is programmed to allow a first error injection onto a first data word using the error injection logic unit. The error injection logic in combination with the content addressable memory unit replaces a bit cell in the memory system. The memory system performs an evaluation of various error detection and correction techniques.