A testing method of electronic devices, each of which includes a central processing unit (CPU) for running an operating system (OS), includes the following steps when testing one of the electronic devices. The specification of the CPU of the electronic device and the version of the OS run on the CPU are identified. A test script of the electronic device is searched from a script lookup table according to the specification of the CPU and the version of the OS. The script lookup table records a variety of test scripts related to the specification of a variety of CPUs of a variety of electronic devices in combination with the version of a variety of operating systems. The found test script is provided to a testing module. The electronic device is tested by the testing module according to the found test script.

A system for testing a design of a computing component includes an input device configured to receive a request to perform a test of a component, and a testing unit including a simulation of the component. The simulation is configured to output a result indicative of a response to a set of instruction addresses, the set of instruction addresses is acquired from a plurality of addresses, and the plurality of addresses including a plurality of address groups, where each address group is associated with a respective group identifier. The system also includes a plurality of requestors configured to apply the set of instruction addresses to the simulation, where a requestor of the plurality of requestors is configured to select an address for application to the simulation based on a received group identifier and a variably configurable weight value assigned to the received group identifier and the requestor.

Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience. Normal processor execution is halted to inject a given state error through a scan chain, and execution is subsequently resumed.

Test code and test data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing test code and test data in the non-naturally aligned data boundaries as described herein allows test code and data to be replicated throughout a cache memory while preserving double word and quad word boundaries in segments of the replicated test code and test data. Coherency of the processor memory can be tested when the same cache line from the level two (L2) cache is simultaneously in both the level one (L1) instruction cache and the L1 data cache.

A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.

Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a second state of executing a self-test sequence of instructions, before returning to the first state of executing the data processing instructions without a reboot of the processor core circuitry being required. There is also self-test support circuitry, wherein the processor core circuitry is responsive to the self-test sequence of instructions to cause an export of at least one self-test data item via the self-test support circuitry to the self-test control circuitry.

Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

A system on a chip including a processor and an in-circuit emulator located within the processor. The processor is to perform processing functions associated with controlling operation of the system on a chip. The in-circuit emulator includes instrumentation logic to take over controlling the operation of the SOC from the processor, perform debugging and emulation functions, and output data including results of the debugging and emulation functions. A frame capture module is to package the data including the results of the debugging and emulation functions into frames having a parallel format. A serializer is to convert the frames from the parallel format to a serial format and output the frames having the serial format from the system on a chip.

A method and a device for testing a computer core in a processor having at least two computer cores is described. The computer cores are connected to each other via an internal connecting system, both computer cores contributing toward the operating sequence of a machine. In the method for testing a computer core, with which a high error detection rate may be achieved in a minimum outlay of time, a test is run in one computer core, while a program for executing the driving operation of the motor vehicle is being processed in the other computer core at the same time.