A central processing unit includes a core, a state memory, a plurality of bus contacts, a data generation unit, and a bus interface unit. The state memory stores a state, the bus interface unit is coupled to the core and the state memory, and the bus interface unit selectively couples the core to the plurality of bus contacts or the data generation unit according to the state.

A method and an apparatus for performing a test for a CPU, and an electronic device. A decay command in a SETWP test and a command-executing duration corresponding to each command subsequent to the decay command can be automatically deployed. Thereby, the SETWP test is correctly performed for the CPU to obtain a test result. It is not necessary to rely on manual adjustment on a parameter of a delay corresponding to each command.

In an approach for a component installation, a processor receives sensor data from a sensor scanning a component. The component is to be installed into a receptacle. A processor compares the sensor data to reference data. The reference data is pre-collected data associated with the type of the component and the type of the receptacle. The reference data defines the correct type of the component to be installed in the receptacle. The reference data defines a damage status of the type of the component. A processor determines whether the component has damage. A processor determines whether the component is a correct type of component to be installed in the receptacle. A processor provides an indication for installation.

A debugging device includes a plurality of debug units, a UART port, and a processor. The debugging device is communicated with an electronic device through the UART port. The processor can receive debug signals from the terminal through the UART port, generate a plurality of debug controlling commands based on the debug signals, and send the plurality of debug controlling commands to the plurality of debug units, for controlling the plurality of debug units to debug the electronic device according to the plurality of debug controlling commands.

Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience. Normal processor execution is halted to inject a given state error through a scan chain, and execution is subsequently resumed.

Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations using multiple lane processing in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations that can leverage multi-lane processing.

A reconfiguration circuit (352) generates a control value for controlling an output value of a control target device based on an input value, and when a fault occurs in an information processing circuit (200) that outputs the control value generated to the control target device, performs preparation for substituting for the information processing circuit (200). Upon completion of the preparation, a reconfiguration target circuit (510) generates an output plan of a control value such that a difference between an actual output value of the control target device and an output value in a scheduled temporal transition gradually decreases, based on the scheduled temporal transition that is a temporal transition of an output value of the control target device, which is scheduled before occurrence of the fault in the information processing circuit (200), a difference between an actual output value of the control target device upon completion of the preparation and an output value in the scheduled temporal transition, and an input value and a control value before occurrence of the fault in the information processing circuit (200), and outputs a control value to the control target device instead of the information processing circuit (200) according to the output plan generated.

The present disclosure is directed to a mechanism for forcing a processor to enter a debug mode. In one embodiment, a processor includes a logic circuit configured to receive a halt request. In response to receiving the halt request while the processor is not in a quiescent state, the logic circuit forces the processor into the quiescent state after a threshold amount of time has elapsed. Processor operation is then halted, and the processor thus becomes accessible for a debugger to perform debug operations.

A system for performing a scan test of a processor core includes a scan test module and a processor including a processor core and an input/output die, where the input/output die is coupled to the processor core. The scan test module transmits, in parallel to the input/output die, scan test input data. A serializer/deserializer module of the input/output die receives the input data, serializes the input data, and transmits the serialized input data to the processor core. A serializer/deserializer module of the processor core receives the serialized scan test input data, deserializes the input data, receives result data generated in dependence upon the input data, serializes the result data, and transmits the serialized result data to the input/output die. The input/output die serializer/deserializer module receives the result data, deserializes the result data, and provides the result data to the scan test module. Error detection can be carried out through redundancy.

The present invention provides a smart overclocking method for a computer device with a multi-core CPU and abasic input/output system (BIOS) where an overclocking database is stored therein, which comprises: booting the computer device, logging in the BIOS and performing an overclocking function; acquiring overclocking parameters from the overclocking database; conducting adjustment/settlement of the clock rate and the voltage of the multi-core CPU based on the overclocking parameters; conducting a Heavy Load Testing (HLT) on the multi-core CPU; reading out working results data of the multi-core CPU and determining whether any of them have exceeded limits. Hence, overclocking can be completed within 10 min. or less, without causing shut down of the computer device, and without causing working temperature or working voltage of multi-core CPU to be higher than 90° C. or 1500 mV during Heavy Load Testing (HLT).