Patent classifications
G06F11/263
Electronic device and non-transitory storage medium implementing test path coordination method
A test path coordination method includes obtaining information of a number of products to be tested, obtaining information of each test device, and planning a test path of each product according to a preset rule according to the information of the products and the information of each test device. The information of the products includes the number of the products, test items of each product, and test devices required for testing the test items. The information of each test device includes whether the test device is currently testing a product and test information of the product currently being tested. The test information of the product includes a length of time the product has been tested and a test result. The test path includes a test sequence of each product and a test sequence of the test items of each product.
METHOD, ARRANGEMENT, AND COMPUTER PROGRAM PRODUCT FOR ORGANIZING THE EXCITATION OF PROCESSING PATHS FOR TESTING A MICROELECTRIC CIRCUIT
The excitation of processing paths in a microelectronic circuit is organized by providing one or more pieces of input information to a decision-making software, and executing the decision-making software to decide, whether one or more of said processing paths of the microelectronic circuit are to be excited with test signals. Deciding that said processing paths are to be excited with said test signals results in proceeding to excite said one or more of said processing paths with said test signals and monitoring whether timing events occur on such one or more excited processing paths. A timing event is a change in a digital value at an input of a respective register circuit on an excited processing path, which change took place later than an allowable time limit defined by a triggering signal to said respective register circuit.
METHOD AND APPARATUS FOR EXTENDING I3C CAPABILITY ACROSS MULTIPLE PLATFORMS AND DEVICES OVER USB-C CONNECTION
Methods and apparatus relating to techniques for extending I3C capability across multiple platforms and devices over a Universal Serial Bus (USB) type C (USB-C) connection are described. In one embodiment, a first device is coupled to a second device via a first interface and a second interface. The first interface is to communicate low-speed messages and data between the first device and the second device and the second interface is to communicate high-speed data between the first device and the second device. The first device comprises an extension controller to communicatively couple one or more target devices of the first device to one or more target devices of the second device via the first interface. Other embodiments are also claimed and disclosed.
METHOD AND APPARATUS FOR EXTENDING I3C CAPABILITY ACROSS MULTIPLE PLATFORMS AND DEVICES OVER USB-C CONNECTION
Methods and apparatus relating to techniques for extending I3C capability across multiple platforms and devices over a Universal Serial Bus (USB) type C (USB-C) connection are described. In one embodiment, a first device is coupled to a second device via a first interface and a second interface. The first interface is to communicate low-speed messages and data between the first device and the second device and the second interface is to communicate high-speed data between the first device and the second device. The first device comprises an extension controller to communicatively couple one or more target devices of the first device to one or more target devices of the second device via the first interface. Other embodiments are also claimed and disclosed.
METHOD AND DEVICE FOR TESTING MICROSERVICE-BASED COMPUTING PLATFORMS
A computer-implemented method for testing a functionality of a computing platform, the computing platform comprising a first microservice, the method comprising: receiving, by an injector microservice, a test configuration file; determining from the test configuration file: a test input message; a test input communication mechanism; and a test output communication mechanism. The method further comprises: generating a test identifier for identifying that a message is being used for testing purposes; transmitting, by the injector microservice, the test input message to the first microservice using the test input communication mechanism, wherein the test input message comprises the test identifier; identifying, by the injector microservice, an output message transmitted via the test output communication mechanism that comprises the test identifier; and recording, by the injector microservice, the output message comprising the test identifier.
METHOD AND DEVICE FOR TESTING MICROSERVICE-BASED COMPUTING PLATFORMS
A computer-implemented method for testing a functionality of a computing platform, the computing platform comprising a first microservice, the method comprising: receiving, by an injector microservice, a test configuration file; determining from the test configuration file: a test input message; a test input communication mechanism; and a test output communication mechanism. The method further comprises: generating a test identifier for identifying that a message is being used for testing purposes; transmitting, by the injector microservice, the test input message to the first microservice using the test input communication mechanism, wherein the test input message comprises the test identifier; identifying, by the injector microservice, an output message transmitted via the test output communication mechanism that comprises the test identifier; and recording, by the injector microservice, the output message comprising the test identifier.
RUNTIME IN-SYSTEM TESTING
During functional/normal operation of an integrated circuit including multiple independent processing elements (such as processors), a selected independent processing element is taken offline (e.g., by stopping functional operation of the independent processing element), and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation (e.g., standard application-specific operations). This enables the selected processing element to be robustly tested without stopping the regular operation of the integrated circuit.
RUNTIME IN-SYSTEM TESTING
During functional/normal operation of an integrated circuit including multiple independent processing elements (such as processors), a selected independent processing element is taken offline (e.g., by stopping functional operation of the independent processing element), and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation (e.g., standard application-specific operations). This enables the selected processing element to be robustly tested without stopping the regular operation of the integrated circuit.
Device maintenance apparatus, device maintenance method, and non-transitory computer readable storage medium
A device maintenance apparatus includes a test executor configured to cause a device to output an output signal based on a test pattern that changes the output signal output from the device with an elapse of time, and a change instructor configured to issue a change instruction for changing at least one of a progress of an output of the output signal based on the test pattern and an output value of the output signal to the test executor in accordance with an instruction input while the test executor causes the device to execute the output of the output signal.
Device maintenance apparatus, device maintenance method, and non-transitory computer readable storage medium
A device maintenance apparatus includes a test executor configured to cause a device to output an output signal based on a test pattern that changes the output signal output from the device with an elapse of time, and a change instructor configured to issue a change instruction for changing at least one of a progress of an output of the output signal based on the test pattern and an output value of the output signal to the test executor in accordance with an instruction input while the test executor causes the device to execute the output of the output signal.