Patent classifications
G06F11/263
Operation management server, development operation support system, method thereof, and non-transitory computer readable medium storing program thereof
An operation management server (20) includes: an associating unit (21) configured to associate an updated content of configuration information of a CMDB (30) with a test scenario corresponding to the updated content; a setting unit (22) configured to set a target system (40) according to the updated content of the configuration information of the CMDB (30); and a test executing unit (23) configured to execute a system test on the set target system (40) based on the test scenario associated with the updated content. This configuration provides an operation management server and a development operation support system capable of easily executing a system test, and a method and a program thereof.
Operation management server, development operation support system, method thereof, and non-transitory computer readable medium storing program thereof
An operation management server (20) includes: an associating unit (21) configured to associate an updated content of configuration information of a CMDB (30) with a test scenario corresponding to the updated content; a setting unit (22) configured to set a target system (40) according to the updated content of the configuration information of the CMDB (30); and a test executing unit (23) configured to execute a system test on the set target system (40) based on the test scenario associated with the updated content. This configuration provides an operation management server and a development operation support system capable of easily executing a system test, and a method and a program thereof.
Automatic framework to create QA test pass
In an aspect of the disclosure, a method, a computer-readable medium, and a device are provided. The device determines one or more feature components of firmware of a BMC to be tested. The device also determines a respective QA category from a plurality of QA categories for each of the one or more feature components. Each of the plurality of QA categories is associated with a set of feature components and a set of the test cases. The device further determines respective at least one test case for each of the one or more feature components based on the respective QA category of the each feature component. The test case specifies hardware and a procedure to be used to test the each feature component.
Automatic framework to create QA test pass
In an aspect of the disclosure, a method, a computer-readable medium, and a device are provided. The device determines one or more feature components of firmware of a BMC to be tested. The device also determines a respective QA category from a plurality of QA categories for each of the one or more feature components. Each of the plurality of QA categories is associated with a set of feature components and a set of the test cases. The device further determines respective at least one test case for each of the one or more feature components based on the respective QA category of the each feature component. The test case specifies hardware and a procedure to be used to test the each feature component.
Electrical testing apparatus for spintronics devices
A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.
Debugging method for USB device and USB device
A debugging method for a Universal Serial Bus (USB) device includes: receiving input information of a terminal through a Human Interface Device (HID) device; when report ID of the input information is a serial port ID, transmitting the input information to a buffer of a virtual serial port Teletype (TTY) device; and extracting the input information of the terminal from the buffer of the virtual serial port TTY device, executing a shell command on the input information, and returning execution result to the terminal through an original path. The method uses a USB interface to implement a HID device, thereby realizing drive-free execution. In addition, use of the endpoint of the HID device can save endpoints needed for additional debugging and driving.
SYSTEMS, APPARATUSES, AND METHODS FOR AUTONOMOUS FUNCTIONAL TESTING OF A PROCESSOR
Systems, methods, and apparatuses for autonomous functional testing of a processor are described. In one example, a processor includes a plurality of processor cores that are each coupled to a respective power management agent circuit; a cache shared by the plurality of processor cores; and a control register, that when set, causes: a save of a state of a first processor core of the plurality of processor cores to storage, a transfer of control of the first processor core to a power management agent circuit of the first processor core, isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, performance of one or more functional tests from the cache on the first processor core caused by the power management agent circuit to generate a test result, removal of the isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, and a transfer of the control by the power management agent circuit back to the first processor core.
SYSTEMS, APPARATUSES, AND METHODS FOR AUTONOMOUS FUNCTIONAL TESTING OF A PROCESSOR
Systems, methods, and apparatuses for autonomous functional testing of a processor are described. In one example, a processor includes a plurality of processor cores that are each coupled to a respective power management agent circuit; a cache shared by the plurality of processor cores; and a control register, that when set, causes: a save of a state of a first processor core of the plurality of processor cores to storage, a transfer of control of the first processor core to a power management agent circuit of the first processor core, isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, performance of one or more functional tests from the cache on the first processor core caused by the power management agent circuit to generate a test result, removal of the isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, and a transfer of the control by the power management agent circuit back to the first processor core.
SYSTEM AND METHOD FOR AUTOMOMOUS TESTING, MACHINE-LEARNING MODEL-SUPERVISED PRIORITIZATION, AND RANDOMIZED WORKFLOW GENERATION
Methods, systems, and computer-readable media are disclosed herein combine randomization functionalities with the machine-learning prioritization of workflows for performance testing. In aspects, a primary workflow having a sequence of user interface steps is input. Testing workflows are generated that represent each variable position of unlocked steps in the sequence of the primary workflow while maintaining the sequential position of any locked steps. These testing workflows are then ingested to a machine learning model that identifies as subset of the testing workflows to prioritize over other. Specifically, testing workflows are prioritized that at least partially match sequence patterns in historical workflow data that is associated with vulnerable computer code. The subset is output and tested by testing engine to generate a report of any vulnerable computer code.
SYSTEM AND METHOD FOR AUTOMOMOUS TESTING, MACHINE-LEARNING MODEL-SUPERVISED PRIORITIZATION, AND RANDOMIZED WORKFLOW GENERATION
Methods, systems, and computer-readable media are disclosed herein combine randomization functionalities with the machine-learning prioritization of workflows for performance testing. In aspects, a primary workflow having a sequence of user interface steps is input. Testing workflows are generated that represent each variable position of unlocked steps in the sequence of the primary workflow while maintaining the sequential position of any locked steps. These testing workflows are then ingested to a machine learning model that identifies as subset of the testing workflows to prioritize over other. Specifically, testing workflows are prioritized that at least partially match sequence patterns in historical workflow data that is associated with vulnerable computer code. The subset is output and tested by testing engine to generate a report of any vulnerable computer code.