Latency of in-system test (IST) execution for a hardware component of an in-field (deployed) computing platform may be reduced when a value of a physical operating parameter can be changed without rebooting the computing platform. A test (e.g., patterns or vectors) is executed for varying values of the physical operating parameter (e.g., supply voltage, clock speed, temperature, noise magnitude/duration, operating current, and the like), providing the ability to detect faults in the hardware components.

A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.

A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.

One embodiment provides a method and a system for generating test vectors for testing a computational system. During operation, the system obtains a design of the computational system, the design comprising an original system. The system generates a design of a fault-augmented system block by adding a plurality of fault-emulating subsystems to the original system; generates a design of an equivalence-checking system based on the original system and the fault-augmented system block; encodes the design of the equivalence-checking system into a logic formula, with variables within the logic formula comprising inputs and outputs of the original system and inputs and outputs of the fault-augmented system block; and solves the logic formula to obtain a test vector used for testing at least one fault in the computational system.

A method of salvaging an output is provided. The method includes defining a condition for terminating a run of a tool, checking whether the condition is likely to be met during a running of the tool, terminating the running in an event the condition is likely to be met, checking a validity of an incomplete output of the tool generated during the running and finalizing the incomplete output in an event the incomplete output is valid.

A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.

A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.

A method, computer program product, and/or system is disclosed for identifying special cases for testing an integrated circuit that includes defining interesting cases, preferably by a user; obtaining an instruction from an instruction set architecture (ISA); determining that there is an interesting case for the obtained instruction; computing (i) a size of the input space (I.sub.0) of the ISA, and (ii) an interesting case space (I.sub.i) which is an input space leading to the interesting case for the obtained instruction; obtaining a special case fraction by dividing the interesting case space (I.sub.i) by the input space (I.sub.0); determining a special case fraction (I.sub.i)/(I.sub.0) is less than a threshold; and identifying, in response to the special case fraction being less than the threshold, the interesting case as a special case. In an approach the special case is documented.

A medical device arrangement (100) tests processing of data sets to be processed during operation of the medical device arrangement. The arrangement includes a data interface (110), analysis modules (120) and a test module (130). The analysis modules process a received medical data set (105). Each analysis module (122, 123, 124) forms a processing instance (390) for the medical data set or for the medical data set (125, 125′) already preprocessed by at least one other analysis module. The test module outputs a test data set (132) to one of the analysis modules during operation such that this analysis module processes the test data set in the same manner as the medical data set. The test module compares a correspondingly outputted, processed test data set (134) with a reference result (136) associated with the test data set and determines a test result (137) based on this comparison.

A medical device arrangement (100) tests processing of data sets to be processed during operation of the medical device arrangement. The arrangement includes a data interface (110), analysis modules (120) and a test module (130). The analysis modules process a received medical data set (105). Each analysis module (122, 123, 124) forms a processing instance (390) for the medical data set or for the medical data set (125, 125′) already preprocessed by at least one other analysis module. The test module outputs a test data set (132) to one of the analysis modules during operation such that this analysis module processes the test data set in the same manner as the medical data set. The test module compares a correspondingly outputted, processed test data set (134) with a reference result (136) associated with the test data set and determines a test result (137) based on this comparison.