The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

In general, a device comprising a processor and a memory may be configured to perform various aspects of the techniques described in this disclosure. The processor may conduct, based on configuration parameters, each of a plurality of simulation iterations within the test environment to collect a corresponding plurality of simulation datasets representative of operating states of the network device. The processor may perform a regression analysis with respect to each of the plurality of configuration parameters and each of the plurality of simulation datasets to generate a light weight model representative of the network device that predicts an operating state of the network device. The processor may output the light weight model for use in a computing resource restricted network device to enable prediction of the operating state of the computing resource restricted network device when configured with the configuration parameters. The memory may store the light weight model.

In general, a device comprising a processor and a memory may be configured to perform various aspects of the techniques described in this disclosure. The processor may conduct, based on configuration parameters, each of a plurality of simulation iterations within the test environment to collect a corresponding plurality of simulation datasets representative of operating states of the network device. The processor may perform a regression analysis with respect to each of the plurality of configuration parameters and each of the plurality of simulation datasets to generate a light weight model representative of the network device that predicts an operating state of the network device. The processor may output the light weight model for use in a computing resource restricted network device to enable prediction of the operating state of the computing resource restricted network device when configured with the configuration parameters. The memory may store the light weight model.

An integrated circuit chip includes a plurality of function blocks; a mode controller configured to convert an input signal, received from an external device through an input/output pin, into an input pattern and test mode setting data which include a plurality of bits, and to output the test mode setting data and a mode switching enable signal when a secure pattern generated therein is the same as the input pattern; and a mode setting module configured to control the plurality of function blocks to operate in a test mode according to the mode setting data, in response to the test mode switching enable signal.

A computer-implemented method is provided for redundancy reduction for driving test scenarios. The method includes receiving an original test set of driving scenarios and a driving model which simulates a vehicle behavior under a driving scenario inputted to the driving model. The method includes, for each driving scenario of the original test set, obtaining vehicle dynamics timeseries data as an output of the driving model. The method includes determining similar driving scenarios by comparing driving model outputs. The method additionally includes creating a new test set of driving scenarios by discarding duplicated ones of the similar driving scenarios from the original test set.

A computer-implemented method is provided for redundancy reduction for driving test scenarios. The method includes receiving an original test set of driving scenarios and a driving model which simulates a vehicle behavior under a driving scenario inputted to the driving model. The method includes, for each driving scenario of the original test set, obtaining vehicle dynamics timeseries data as an output of the driving model. The method includes determining similar driving scenarios by comparing driving model outputs. The method additionally includes creating a new test set of driving scenarios by discarding duplicated ones of the similar driving scenarios from the original test set.

A parallel processing system includes at least three processors operating in parallel, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.

A parallel processing system includes at least three processors operating in parallel, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.

A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.