A system, method, and computer program are provided for combining results of event processing received from a plurality of virtual processes or servers. In use, an event is sent to a plurality of virtual processes or virtual servers. Further, a result of processing of the event is received from each of the virtual processes or virtual servers. In addition, the results received from the plurality of virtual processes or virtual servers are combined.

Various embodiments include components (e.g., a processor in a vehicle advanced driver assistance system) configured to identify subsystems that require testing in order to verify their compliance with a safety requirement. The components may determine whether verification of compliance requires that the subsystems be tested at PON, at POFF, during runtime or a combination thereof, dynamically determine the achievable parallelism for testing the identified subsystems, dynamically determine coverage level requirements for performing or executing built in self tests (BISTs) on each identified subsystem, and perform or execute the BISTs on the subsystems at the determined level of parallel and at the determined coverage level.

In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

A semiconductor device includes a debug port, a first access port, a second access port, a first processing unit, a second processing unit, and an embedded emulator unit. The first access port is coupled to the debug port. The second access port is coupled to the debug port. The first processing unit is coupled to the first access port. The second processing unit is coupled to the second access port. The embedded emulator unit is coupled to the debug port, the first processing unit and the second processing unit. The first processing unit generates a debug instruction to access the embedded emulator unit, so that the embedded emulator unit generates a debug signal. The debug signal is output to the second processing unit through the debug port and the second access port, so as to perform a debug operation on the second processing unit.

A semiconductor device includes a debug port, a first access port, a second access port, a first processing unit, a second processing unit, and an embedded emulator unit. The first access port is coupled to the debug port. The second access port is coupled to the debug port. The first processing unit is coupled to the first access port. The second processing unit is coupled to the second access port. The embedded emulator unit is coupled to the debug port, the first processing unit and the second processing unit. The first processing unit generates a debug instruction to access the embedded emulator unit, so that the embedded emulator unit generates a debug signal. The debug signal is output to the second processing unit through the debug port and the second access port, so as to perform a debug operation on the second processing unit.

Various embodiments described herein provide for in-service scanning and correction of stored data for achieving functional safety. For some embodiments, a data scanning and correction system periodically reads data from different portions (e.g., addresses) of a storage device (e.g., memory) implemented with ECC to detect any errors in the data. If an error is detected, the data scanning and correction system generates corrected data and rewrites the corrected data to the portion of the storage device. The data scanning and correction system may continuously cycle this process through different portions of the storage device to detect and correct errors while the storage device is in-service.

Examples described herein provide a method for testing a memory associated with a processing system of an aircraft. The method includes performing, during operation of the processing system, an operational built-in test on the memory. The method further includes, responsive to detecting an error in the memory during the operational built-in test, performing a focused memory test at a location in the memory of the error. The method further includes, responsive the error being confirmed by the focused memory test, causing the processing system to be taken offline.

It is possible to intuitively identify the reason for the handshake failure. An entire state transition flow including each state based on the communication standard and a state transition condition to be executed between states is displayed as a state transition setting screen 11, and an immediately preceding state in which the state transition fails and the failed state transition condition are highlighted on the state transition setting screen 11, when the handshake with the device under test ends.

It is possible to intuitively identify the reason for the handshake failure. An entire state transition flow including each state based on the communication standard and a state transition condition to be executed between states is displayed as a state transition setting screen 11, and an immediately preceding state in which the state transition fails and the failed state transition condition are highlighted on the state transition setting screen 11, when the handshake with the device under test ends.