A computer-implemented method for of constrained carries on speculative counters includes providing one or more speculative counters having an upper portion of most significant bits partially embedded in a random-access memory (RAM) array, and a pre-counter portion external to the RAM array having a plurality of least significant bits. The one or more speculative counters are configured to count a plurality of events of interest during a processor core instruction execution. A carry output from the pre-counter portion to the RAM array is suppressed for a duration of a speculative event period.

In an information processing apparatus, a control unit receives operation instructions. Each time receiving an operation instruction, the control unit detects the number of operating circuits that are to operate in accordance with the received operation instruction, in a circuit group of circuits that operate in synchronization with a clock signal. In addition, each time receiving an operation instruction, the control unit determines whether power supply noise that is likely to cause a timing error in the circuit group will occur, on the basis of a result of comparing an increase in the number of operating circuits per prescribed time period with a threshold, and lowers the frequency of the clock signal when determining that the power supply noise will occur.

Aspects of the disclosure provide for mechanisms for memory protection of virtual machines in a computer system. A method of the disclosure includes: determining a plurality of host latency times for a plurality of processor power states of a processor of a host computer system; comparing, by a hypervisor executed on the host computer system, each of the host latency times to a target latency time associated with a virtual machine running on the host computer system; mapping the plurality of processor power states to a plurality of host power states in view of the comparison; and providing the host power states to the virtual machine.

A method for controlling and/or monitoring a machine arrangement having at least one machine, in particular at least one robot, with the aid of a processor arrangement having a plurality of processors each with at least one core. The method includes selecting, in particular temporarily selecting, a first available and at least one further available core on the proviso that these cores are implemented, in particular arranged, on different processors of the processor arrangement, in particular during operation of the machine arrangement and/or on the basis of an updated directory and/or on the basis, in particular as a result, of an ascertained need for redundant processing of process signals; processing process signals redundantly with the aid of these selected cores; and controlling and/or monitoring the machine arrangement on the basis of this processing.

An accelerator circuit including a control interface to receive a stream of instructions, a first memory to store an input data, and an engine circuit including a dispatch circuit to decode an instruction of the stream of instructions into a plurality of commands, a plurality of queue circuits, each of the plurality of queue circuits supporting a queue data structure to store a respective one of the plurality of commands decoded from the instruction, and a plurality of command execution circuits, each of the plurality of command execution circuits to receive and execute a command extracted from a corresponding one of the plurality of queues.

In computer-implemented method, computer system, and/or computer program product, a processor(s) obtains a test (of steps(s)) to verify program code for deployment in distributed computing system. The processor(s) determines pre-defined operations correlating to the step(s). The processor(s) automatically distributes the pre-defined operations to a resources of a distributed computing system, for execution. The processor(s) monitors the execution and saves at least one screenshot as each step. The processor(s) generates a user interface with a status indicator. The processor(s) continuously update the user interface, based on the monitoring, to reflect a progression of the portion of the one or more resources through the step(s).

A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

A cache and memory coherent system includes multiple processing chips each hosting a different subset of a shared memory space and one or more routing tables defining access routes between logical addresses of the shared memory space and endpoints that each correspond to a select one of the multiple processing chips. The system further includes a coherent mesh fabric that physically couples together each pair of the multiple processing chips, the coherent mesh fabric being configured to execute routing logic for updating the one or more routing tables responsive to identification of a first processing chip of the multiple processing chips hosting a defective hardware component, the update to the routing tables being effective to remove all access routes having endpoints corresponding to the first processing chip.

A capacitive intelligent workstation detection system, comprising a capacitance detection sensor (1), a capacitive sensing module (201), a microprocessor module (202), a remote management platform (3) and a mobile APP, the capacitance detection sensor (1) detecting a capacitance change when a human body approaches, and after being processed by the capacitive sensing module (201), the capacitance change being sent to the microprocessor module (202) to form workstation state data, the workstation state data being sent to the remote management platform (3), and the remote management platform (3) processing the workstation state data, so as to obtain user habit data. A user uses the mobile APP to obtain relevant data by means of the remote management platform (3), and sends debugging and control information to a workstation detection device (2). The system uses the capacitive sensing module (201), has a small volume, a good concealment, a beautiful appearance and a flexible design, does not require complex optical and microwave devices and has no mechanical device, is less vulnerable to aging and abrasion, and has a long service life and good consistency. The remote management platform (3) serves as a data management and control center, and the mobile APP provides man-machine bidirectional interaction, so as to implement office electric appliance linkage energy-saving management and personnel management.

An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes a first processor for executing a custom BMC firmware stack, and transmitting a watchdog message at an ongoing basis. The BMC also includes a second processor for receiving the watchdog message. When the watchdog message is received within a specified elapsed period of time, allow continued operation of the custom BMC firmware stack, and when not received within the specified elapsed period of time, place the BMC in a failsafe mode of operation.