A cyber security system for in-vehicle networks comprises a plurality of electronic control units (ECUs) communicating via a vehicle bus. The system comprises a plurality of bus security units (BSUs), wherein each BSU is configured to be connected between the vehicle bus and one of the ECUs, and the BSUs communicating via a security bus separate from the vehicle bus. Each BSU is configured to monitor the activity of the corresponding ECU, on the vehicle bus, send the monitored activity to another BSU on the security bus and detect abnormal communication on the vehicle bus.

A perception processing system includes a memory and a main controller. The main controller includes modules and implements a data processing pipeline including algorithm stages, which are executed in parallel relative to sets of data and are executed sequentially relative to each of the sets of data. The algorithm stages share resources of the modules and the memory to process the sets of data and generate perception information. One of the modules executes global and local controllers. The global controller sets a processing rate for the local controllers. The local controllers monitor current processing rates of the algorithm stages. When one of the current processing rates is less than the set processing rate, the corresponding one of the local controllers sends a first signal to the global controller and in response the global controller sends a broadcast signal to the local controllers to adjust the current processing rates.

Managing HDD performance at an IHS, including determining, for each write operation, a total number of revolutions of a disk of a HDD to complete the write operation and a number of revolutions of the disk of the HDD during the write operation that a write head of the HDD is off-track; calculating, for each write operation, a performance loss of the HDD; determining an average performance loss (APL) of the HDD over a first time period based on the performance loss of each write operation performed for the first time period; determining that the APL of the HDD over the first time period is greater than the threshold, and in response, performing a mitigation service at the IHS.

An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster. In some implementations, the power management processor receives, from a system controller external to the plurality of processing clusters, a first power allocation for the first processing cluster.

A method for determining a faulty computing core in a multi-core processor and an electronic device are provided. The method is applied to an electronic device configured with a multi-core processor. The multi-core processor is integrated with a plurality of computing cores, the plurality of computing cores are independent of each other, and the plurality of computing cores include a first computing core. The method includes: determining a computing core corresponding to each of N running exceptions, where the running exception is caused by an exception that occurs when any computing core in the plurality of computing cores executes the program instructions (301); and when a quantity of running exceptions corresponding to the first computing core in the N running exceptions is greater than or equal to M, determining that the first computing core is a faulty computing core, where M is a preset value (303).

A method of processing a workload in a graphics processing unit (GPU) may include detecting a work item of the workload in the GPU, determining a cache policy for the work item, and operating at least a portion of a cache memory hierarchy in the GPU for at least a portion of the work item based on the cache policy. The work item may be detected based on information received from an application and/or monitoring one or more performance counters by a driver and/or hardware detection logic. The method may further include monitoring one or more performance counters, wherein the cache policy for the work item may be determined and/or changed based on the one or more performance counters. The cache policy for the work item may be selected based on a runtime learning model.

A computer-implemented method is presented for reporting application programs linked to by an application running under an online transaction processor of a mainframe computing environment. An intercept program is implanted in an address space of the online transaction processor. A task executing outside of the address space of the online transaction processor identifies an address for a target domain gate program supported in a domain by the online transaction processor; identifies an address for an unused domain gate program supported in the domain by the online transaction processor; replaces the address for the unused domain gate program with the address for the target domain gate program; and replaces the address for the target domain gate program with an address for the intercept program.

The present disclosure relates to generating a filtered data set. Data from a plurality of systems of record of a plurality of data source providers may be accessed. A master data set generated using the data accessed from the plurality of systems of record may be maintained. Restriction policies including one or more rules for restricting sharing of data may be maintained. A filtered data set may be generated for a data source provider responsive to an application of restriction policies of other data source providers to the master data set. The filtered data set may be provisioned.

A semiconductor device includes a clock circuit that outputs a clock signal of a first frequency, a detection circuit that detects occurrence of power supply noise and end of the power supply noise, and a control circuit. The control circuit drops, in a case where the occurrence of the power supply noise is detected, a frequency of the clock signal from the first frequency to a second frequency, determine a frequency return time according to a noise occurrence time from the occurrence of the power supply noise to the end of the power supply noise, and returns the frequency of the clock signal from the second frequency to the first frequency on the basis of the frequency return time.

Adaptive power management of a computing device is provided such that computer power can be dynamically allocated and adjusted among CPU and other power consuming peripherals based on the power usage pattern of individual users. Power overuse (surge and/or agency) events occurred during a time period (e.g., a week) are recorded in a database. By analyzing the recorded power overuse events, the computing device can be operated under a customized power budget profile learned from the user's power usage pattern, allowing different weight to different power consuming components, so as to optimize the performance of the computing device based on the usage scenario of different users at different time.