A cyber security system for in-vehicle networks comprises a plurality of electronic control units (ECUs) communicating via a vehicle bus. The system comprises a plurality of bus security units (BSUs), wherein each BSU is configured to be connected between the vehicle bus and one of the ECUs, and the BSUs communicating via a security bus separate from the vehicle bus. Each BSU is configured to monitor the activity of the corresponding ECU, on the vehicle bus, send the monitored activity to another BSU on the security bus and detect abnormal communication on the vehicle bus.

Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBD technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBL

System and method for fault identification and fault handling in MPSD are provided. The system includes: a multi-port power sourcing device including multiple ports, a master is configured to: send a slave discovery request to multiple slave ports, receive a slave discovery response from the multiple slave ports; reset the watchdog timer in the multiple ports by sending watchdog refresh instruction periodically; each of the multiple ports experience watchdog timer timeout upon failing to receive the watchdog refresh instruction, generate their corresponding port reset upon watchdog timer timeout, to resolve one or more faults associated with the corresponding port; the multiple ports include a role change staggered timer which is triggered upon the corresponding watchdog timer timeout, and reset upon receiving the watchdog refresh instruction from master; the slave ports for which role change staggered timer times out first, changes the role to start functioning as the new master port.

A security device connected to a plurality of networks in a vehicle is provided. The security device determines, with regard to a frame received from a first network, whether to transmit a determination request for the frame outside the vehicle. The security device transmits the determination request outside the vehicle in a case where it is determined to transmit the determination request outside the vehicle, transmits, before obtaining a determination result from outside the vehicle in accordance with the determination request, the frame to a second network, and then obtains determination results from outside the vehicle in accordance with the determination request. The security device outputs presentation information in accordance with the determination result.

A Peripheral Component Interconnect Express (PCIe) interface device coupled to an external device through a link including a plurality of lanes according to the present disclosure includes an EQ controller controlling the PCIe interface device to perform an equalization operation for determining a transmitter or receiver setting of each of the plurality of lanes, and an EQ information storage storing log information indicating a number of equalization operation attempts with respect to each of a plurality of EQ coefficients and storing error information about an error occurring in an LO state with respect to each of the plurality of EQ coefficients, which includes a transmitter coefficient or a receiver coefficient, wherein the EQ controller determines a final EQ coefficient using the log information and the error information.

A serial communication link receiver-transmitter with autonomous transmission error detection is described, and a communication peripherals including the same. Transmit data at a transmitter and transmitted data output by the transmitter and received by the receiver are observed by an error detector configured to generate an error indication in response to difference between the transmit data and corresponding observed transmit data of a transmitted data frame. If a difference is detected a transmit error indicator is asserted.

A method of performing error detection within an integrated circuit chip analyses transactions communicated over interconnect circuitry of the integrated circuit chip to detect whether a message contains a data error. A memory of the integrated circuit chip coupled to the interconnect circuitry is scanned to detect whether there is a data error stored in the memory, and in response to detecting a data error in a transaction communicated over the interconnect circuitry and/or a data error stored in the memory, a dedicated action indicative of a data error is performed.

A device and method for communication among vehicle components operating on different electronic vehicle bus communication protocols is disclosed. The current invention is specifically designed with the capabilities and reliability required for permanent integration of an incompatible device into a vehicle bus network. This allows for installation and permanent integration of incompatible devices onto new and advanced vehicles which are manufactured using the latest electronic vehicle bus communication protocols.

A test device and a method are provided in the invention. The test device includes a first connection interface, a storage device, a processor and a second connection interface. The first connection interface is coupled to a device under test (DUT) and obtains power information from the DUT according to a first instruction. The storage device stores the power information. The processor is coupled to the first connection interface and storage device, when the first connection interface is coupled to the DUT, sends the first instruction to the first connection interface, receives the power information from the first connection interface, and stores the power information in the storage device. The second connection interface is coupled to an external controlling system, sends the power information to the external controlling system and receives a test instruction from the external controlling system to test the DUT.

A memory control device includes a memory control part that controls memory through an interface part in accordance with a predetermined communication regulation, an illegal access detection part that detects an illegal access to the memory according to an access state from the memory control part to the memory and a signal state of the interface part, and a signal control part that switches the signal state of the interface part from a write-allowed state, in which the interface part is able to be written, to a write-inhibited state, in which the interface part is protected from being rewritten, when the illegal access is detected by the illegal access detection part.