A processing system includes an interconnect fabric coupleable to a local memory and at least one compute cluster coupled to the interconnect fabric. The compute cluster includes a processor core and a cache hierarchy. The cache hierarchy has a plurality of caches and a throttle controller configured to throttle a rate of memory requests issuable by the processor core based on at least one of an access latency metric and a prefetch accuracy metric. The access latency metric represents an average access latency for memory requests for the processor core and the prefetch accuracy metric represents an accuracy of a prefetcher of a cache of the cache hierarchy.

This invention discloses a data processing circuit and a data processing method. The data processing method controls data transmission between a USB control unit and a USB interface, and includes the steps of: detecting a voltage of a configuration channel pin of the USB interface to generate a detection signal; determining whether the USB control unit and the USB interface are connected according to the detection signal; and performing an audio signal processing procedure when the USB control unit and the USB interface are not connected.

Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.

A circuit apparatus includes physical layer circuits to which buses compliant with the USB standard are coupled, a processing circuit that performs an FS transfer process, a bus monitoring circuit that monitors the buses, and a bus switching circuit that turns on or off the coupling between a first bus and a second bus based on the result of the monitoring. One of the physical layer circuits includes an FS receiver, an FS driver, and a pull-up control circuit, and the other physical layer circuits includes an FS receiver and an FS driver. When FS_J is detected on the second bus, the bus monitoring circuit turns off the coupling achieved by the bus switching circuit, turns on the pull-up operation performed by the pull-up control circuit, and turns on the FS transfer process performed by the processing circuit.

A storage system includes: a power source; a drive box that stores a storage apparatus; a storing apparatus having a storage unit in which data regarding devices is stored; a PCIe switch that can switch between a plurality of communication paths, has a communication path connected at least to the storage apparatus, and can further perform I2C communication with the storing apparatus; an auxiliary apparatus that can perform I2C communication with the PCIe switch; and a MOS switch that controls power supply from the power source to the storing apparatus, wherein if timeout of the I2C communication between the PCIe switch and the storing apparatus occurs, the PCIe switch transmits a hard reset command to the auxiliary apparatus; and wherein when the auxiliary apparatus receives the hard reset command, the auxiliary apparatus stops the power supply to the storing apparatus by using the MOS switch and then performs power resupply.

Facilitating ad hoc daisy-chaining of dynamically addressable devices having configurable physical layer interfaces together in a serial manner is presented herein. A system can include a group of devices communicatively coupled with respective devices of the group of devices in a daisy-chained manner via physical layer (PHY) interfaces of the respective devices including a group of available communication protocol configurations including a low voltage differential signaling (LVDS) based PHY configuration, a controller area network (CAN) based PHY configuration, and/or a single-ended serial communication PHY configuration including a complementary metal-oxide-semiconductor (CMOS) based interface or a transistor-transistor logic (TTL) based interface. Further, a host device of the system is directly connected, using a single-ended Manchester encoded serial communication interface, to a foremost device of the group of devices and to successive devices of the respective devices, via the foremost device, using the single-ended Manchester encoded serial communication interface.

In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.

A method for determining a connection status of a device to a cable within a network environment is provided. The method comprises obtaining a signal from a non-data carrying wire of the cable by a detector that is digitally isolated from data transmitted in a data carrying wire of the cable within the network environment, modifying the signal transmitted by the non-data carrying wire to the device and evaluating the modified signal to determine a connection status of the device to the cable.

A circuit apparatus includes physical layer circuits to which buses compliant with the USB standard are coupled, a processing circuit that performs an FS transfer process, a bus monitoring circuit that monitors the buses, and a bus switching circuit that turns on or off the coupling between a first bus and a second bus based on the result of the monitoring. One of the physical layer circuits includes an FS receiver, an FS driver, and a pull-up control circuit, and the other physical layer circuits includes an FS receiver and an FS driver. When FS_J is detected on the second bus, the bus monitoring circuit turns off the coupling achieved by the bus switching circuit, turns on the pull-up operation performed by the pull-up control circuit, and turns on the FS transfer process performed by the processing circuit.

A method and a system for processing a data conflict are provided that relate to the field of signal interface technologies of an integrated circuit, where the method includes sending a power management bus (PMBus) command to a slave device by using a PMBus, so as to perform power management; when the PMBus command fails to be sent, determining whether the number of times that the PMBus command fails to be sent is greater than or equal to a preset value, where the preset value is configured in advance during system initialization; starting timing if the number of times that the PMBus command fails to be sent is less than the preset value; and resending the PMBus command when timing duration reaches resending time. The present invention is applicable to a scenario in which multiple master devices (Masters) send the PMBus command by using the PMBus.