Patent classifications
G06F11/3031
TEMPERATURE INCREASING DEVICE AND TEMPERATURE INCREASING METHOD
The application provides a temperature increasing device and a temperature increasing method. The temperature increasing device is arranged on a motherboard including at least one system element. The temperature increasing device includes a power supply module and a controller After the power supply module is triggered, the power supply module outputs an enable signal to the system element and the controller, the controller detects whether the system element operates according to a preset power-on action, if the controller determines that the system element does not operate according to the preset power-on action, the controller outputs an electric signal to enable the temperature of the system element to increase, and when the temperature of the system element is increased to an extent that the controller determines that the system element is capable of operating according to the preset power-on action, the controller stops outputting the electric signal.
Low-Overhead, Bidirectional Error Checking for a Serial Peripheral Interface
Example embodiments relate to low-overhead, bidirectional error checking for a serial peripheral interface. An example device includes an integrated circuit. The device also includes a serial peripheral interface (SPI) with a Master In Slave Out (MISO) channel and a Master Out Slave In (MOSI) channel. The MOSI channel is configured to receive a write address, payload data, and a forward error-checking code usable to identify data corruption within the write address or the payload data. The integrated circuit is configured to calculate and provide a reverse error-checking code usable to identify data corruption within the write address or the payload data. Additionally, the integrated circuit is configured to compare the forward error-checking code to the reverse error-checking code. Further, the integrated circuit is configured to write, to the write address if the forward error-checking code matches the reverse error-checking code, the payload data.
Independent thermal throttling temperature control for memory sub-systems
A system includes a memory device of multiple devices, and a processing device of the multiple devices, coupled with the memory device. The system identifies multiple device temperature values that are each indicative of a temperature at a respective device of the multiple devices of the system. The system determines that at least one device temperature value of the multiple device temperature values satisfies a respective thermal throttling threshold of multiple thermal throttling thresholds. The system performs a power reducing operation to reduce a power consumption of the system in accordance with a power reduction value based on the satisfaction of the respective thermal throttling threshold.
System and method for data logging within a field replacement unit
A computer-implemented method, computer program product, and computing system for detecting the availability of status-related data within an FRU. The status-related data is written to persistent memory within the FRU.
Method and apparatus for data recovering during a board replacement
A management controller is disclosed. The management controller may include a receiver to receive a request from an initiator. A translator may translate the request received from the initiator into a command for a multi-mode single port device. A bridge may communicate with the multi-mode single port device and the initiator, sending the command to the multi-mode single port device and receiving a reply from the multi-mode single port device. The translator may then translate the reply to the command into a response for the initiator, whereupon a transmitter may transmit the response to the initiator.
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM
An information processing device includes a processor; and an offload circuit coupled to the processor via links, the offload circuit including: a first circuit that computes processes of applications, a second circuit that collects values indicating performance information of the links for flows corresponding to the processes of the applications and maximum values indicated in performance information and usable by the links, and a third circuit that determines a flow not satisfying requested performance information based on the values indicating the performance information of the links for the flows, selects a link to which the flow is to be allocated, based on the maximum values indicated in the performance information and usable by the links and values indicated in performance information and currently used by the links, and allocates the flow to the selected link.
Storage system based host computer monitoring
The present invention includes establishing, by a storage system coupled to a first host computer via a storage area network (SAN), metrics indicating a status of the first host computer, and storing the indicated metrics to the storage system. A second host computer, coupled to the storage system via the storage area network, determines an availability of the first host computer based on the metrics.
Storage system based host computer monitoring
Methods, apparatus and computer program products implement embodiments of the present invention that include establishing, by a storage system coupled to a first host computer via a storage area network (SAN), metrics indicating a status of the first host computer, and storing the indicated metrics to the storage system. A second host computer, coupled to the storage system via the storage area network, determines an availability of the first host computer based on the metrics.
METHODS AND APPARATUS TO COMMUNICATIVELY COUPLE FIELD DEVICES TO A REMOTE TERMINAL UNIT
Methods and apparatus to communicatively coupled field devices to a remote terminal unit are disclosed. The example apparatus includes a base rack for a remote terminal unit in a process control system. The example apparatus further includes a first termination module to be inserted in a first termination slot of the base rack. Wires communicatively coupled to a field device are to be terminated on the first termination module. The example apparatus also includes a first control module separate from the first termination module to be inserted in a first control slot of the base rack. The first control module is to be communicatively coupled with the first termination module via a backplane of the base rack. The first control module is to control communications with the field device.
SELECTION OF A LOCATION FOR INSTALLATION OF A CPU IN A COMPUTE NODE USING PREDICTED PERFORMANCE SCORES
A computer program product may include storage media embodying program instructions executable by a baseboard management controller (BMC) within a compute node to: receive a request to install a central processing unit (CPU) in the compute node; identify a current hardware configuration of the compute node; identify a plurality of available locations within the compute node that are compatible with installation of the CPU; calculate, for each of the identified plurality of available locations, a predicted performance score for the CPU on the basis that the CPU were to be installed in the available location, wherein the predicted performance scores are calculated in response to receiving the request; select a location from among the plurality of available locations that is associated with the greatest performance score for the CPU; and generate user output indicating the selected location where the CPU should be installed.