In some examples, a system records, in a data structure stored in a non-volatile storage, information of memory errors in respective segments of a memory. The system determines whether memory errors of a subset of the segments satisfy a criterion, and in response to determining that the memory errors of the subset of the segments satisfy the criterion, the system groups the memory errors of the subset into a partition having a size greater than a size of a segment. The system records, in the data structure, information of memory errors in the partition, and in response to a restart of the system, retrieves the data structure from the non-volatile storage for use in an operation that addresses memory errors in the system.

An average inter-pulse delay of a data unit of the memory device is calculated. An average temperature of the data unit is calculated. A first scaling factor based on the average inter-pulse delay and a second scaling factor based on the average temperature is obtained. A media management metric based on the first scaling factor and the second scaling factor is calculated. Responsive to determining that the media management metric satisfies a media management criterion, a media management operation on the data unit at a predetermined cycle count is performed.

A method, a system, and a computer program product for placement or storage of data structures in memory/storage locations. A type of a data structure for storing data and a type of data access to the data structure are determined. The type of data access includes a first and a second type of data access. A frequency of each type of access to each type of data structure accessed by a query is determined. Using the determined frequency, a number of first type of data accesses to the data structure is compared to a number of second type of accesses to the data structure. The numbers of first and second types of data access are compared to a predetermined threshold percentage of a total number of data accesses to the data structure. Based on the comparisons, a physical memory location for storing data is determined.

A system includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing, during chip initialization, a first attempt of a chip initialization process to be performed based on a first configuration. The first configuration includes a first set of control settings for reading a block of the memory array during the first attempt. The operations further include determining that the first attempt has failed, and, in response to determining that the first attempt has failed, causing an automatic chip initialization retry process to be performed. Causing the automatic chip initialization retry process to be performed includes causing a second attempt of the chip initialization process to be performed using a second configuration. The second configuration includes a second set of control settings different from the first set of control settings for reading the block during the second attempt.

A semiconductor memory apparatus may include: a memory cell array; an ECC (Error Check and Correction) circuit configured to detect an error from data read from the memory cell array in response to a read command, correct the detected error, and output an error correction signal whenever an error is corrected; and an EF (Error Flag) generator configured to enter a flag output mode when the number of times that the error correction signal is generated during a monitoring period reaches a threshold, and output the error correction signal as an error flag in the flag output mode.

Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

A method of error management includes, in response to a read request for first data from a first storage device of a plurality of storage devices under one or more common data protection schemes, receiving a read uncorrectable indication regarding the first data, obtaining uncorrected data and metadata of an LBA associated with the first data, and obtaining the same LBA from one or more other storage devices of the plurality. The method further includes comparing the uncorrected data with the data and metadata from the other storage devices, speculatively modifying the uncorrected data based, at least in part, on the other data to create a set of reconstructed first data codewords, and, in response to a determination that one of the reconstructed first data codewords has recovered the first data, issuing a write_raw command to rewrite the modified data and associated metadata to the first storage device.

An operating method of a memory system including a memory device including a plurality of memory chips is provided. The operating method includes setting a parameter indicating a number of the memory chips allowed to operate in parallel for each of a plurality of operation statuses, based on information about power consumption of each of the plurality of operation statuses of a memory chip among the memory chips; obtaining information about an operation status of each of the plurality of memory chips; and scheduling data access across a plurality of channels respectively corresponding to the plurality of memory chips, based on the parameter and the information about the operation status of each of the plurality of memory chips.

An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells arranged along word lines. The one or more control circuits are configured to receive a plurality of encoded portions of data to be programmed in non-volatile memory cells of a target word line, each encoded portion of data encoded according to an Error Correction Code (ECC) encoding scheme, and arrange the plurality of encoded portions of data in a plurality of rows of data latches corresponding to a plurality of logical pages such that each encoded portion of data is distributed across two or more rows of data latches. The one or more control circuits are also configured to program the distributed encoded portions of data from the plurality of rows of data latches into non-volatile memory cells along a target word line.

Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes one or more computing resources and a memory controller coupled to a memory device. The memory controller determines a memory access request targets a given bank of multiple banks. An access history is updated for the given bank based on whether the memory access request hits on an open page within the given bank and a page hit rate for the given bank is determined. The memory controller sets an idle cycle limit based on the page hit rate. The idle cycle limit is a maximum amount of time the given bank will be held open before closing the given bank while the bank is idle. The idle cycle limit is based at least in part on a page hit rate for the bank.