The present disclosure relates to a method for electronic design verification. Embodiments may include identifying a plurality of higher level instances along an electronic design path from a source to a destination. Embodiments may further include analyzing inter-instance path information associated with the plurality of higher level instances included in the electronic design path from source to destination. Analyzing may include ignoring information included within the plurality of higher level instances. Embodiments may further include determining, based upon, at least in part, inter-instance path information whether data is unable to propagate from the source to the destination.

Embodiments are disclosed for a method. The method includes identifying a prefix updated by a searcher of a machine learning model. The machine learning model is configured to generate source code in a programming language. The method also includes determining whether the prefix violates a semantic correctness property of the programming language. Additionally, the method includes instructing the searcher, in response to the determination, to prune the prefix from a set of prefixes under consideration by the searcher.

Implementations are disclosed for facilitating visual programming of machine learning state machines. In various implementations, one or more graphical user interfaces (GUIs) may be rendered on one or more displays. Each GUI may include a working canvas on which a plurality of graphical elements corresponding to at least some of a plurality of available logical routines are manipulable to define a machine learning state machine. One or more of the available logical routines may include logical operations that process data using machine learning model(s). Two or more at least partially redundant logical routines that include overlapping logical operations may be identified, and overlapping logical operations of the two or more at least partially redundant logical routines may be merged into a consolidated logical routine. At least some of the logical operations that were previously downstream from the overlapping logical operations may be logically coupled with the consolidated logical routine.

In an approach to improve detecting and correcting errors in one or more machine learning pipelines. Embodiments comprise generating a plurality of test machine learning pipeline instances based upon a target machine learning pipeline and evaluating the plurality of test machine learning pipeline instances for failure in a task. Further, embodiments identify one or more root causes of error based upon the evaluated plurality of test machine learning pipeline instances and failure in the task, and create a remediated target machine learning pipeline based upon the identified one or more root causes of error. Additionally, embodiments output the remediated machine learning pipelines.

The disclosed embodiments include methods and systems for providing predictive quality analysis. Consistent with disclosed embodiments, a system may receive input data associated with a software program and compare the input data with one or more predetermined analysis parameters. The system may further determine at least one risk rating based on the comparison, wherein each risk rating corresponds to a distinct software category. The system may perform additional operations, including determining at least one adjustment to the software program based on the determined at least one risk rating, and prioritizing the at least one adjustment based on a predetermined adjustment priority standard. Furthermore, the system may provide a report including at least an indication of the at least one prioritized adjustment, a timeline for implementing the at least one prioritized adjustment, and plan implementing the at least one prioritized adjustment.

A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

Systems and methods for censoring text characters in text-based data are provided. In some embodiments, an artificial intelligence system may be configured to receive text-based data and store the text-based data in a database. The artificial intelligence system may be configured to receive a list of target pattern types identifying sensitive data and receive censorship rules for the target pattern types determining target pattern types requiring censorship. The artificial intelligence system may be configured to assemble a computer-based model related to a received target pattern type in the list of target pattern types. The artificial intelligence system may be configured to use a computer-based model to identify a target data pattern corresponding to the received target pattern type within the text-based data, identify target characters within the target data pattern, and to assign an identification token to the target characters.

Systems and methods for tracking and ranking errors in computer systems may be used in e-commerce applications in order to identify errors that occur in e-commerce user sessions along with an estimate of potential lost revenues resulting from the error. The errors and associated lost revenues may allow prioritizing of which errors to address.

It is disclosed a PLC Program analysis method where a program is translated into a program model in a logical framework, from which properties are determined. Said properties coupled with interlocking properties are verified by an automated solver. If contraposition of a property is satisfiable, counter-examples representative of model's inputs and internal memory values is provided. Counter-examples are translated into error initial configurations of said model. Execution of the model is simulated with said model error initial configurations, and error intermediary configurations of said model simulation are recorded up to said property violation. Error initial and intermediary configurations of said original program are derived from error initial configurations of said model and error intermediary configurations of said model simulation and displayed. An apparatus for executing said method is provided.

A method for analyzing a computer program ecosystem includes performing a static analysis, including identifying static dependencies among elements of the ecosystem based on values of parameters in one or more parameter sets associated with the ecosystem, the elements of the ecosystem including the computer programs of the ecosystem and data resources associated with the computer programs. The method includes performing a runtime analysis, including identifying elements of the ecosystem that were utilized during execution of the ecosystem to process data records. The method includes performing a schedule analysis, including identifying a computer program of the ecosystem that has a schedule dependency from another computer program of the ecosystem. The method includes identifying a subset of the elements of the ecosystem as an ecosystem unit based on the results of the static, runtime, and schedule analyses. The method includes migrating the ecosystem unit, testing the ecosystem unit, or both.