A method includes assessing an input in a buffer against a rule in a first node of a rule tree to determine that an action should be performed and updating the buffer with results of performing the action. The method also includes inserting an indication of the input, the rule, and the results of performing the action into a tracker log and passing the updated buffer to a second node in the rule tree in response to determining that the first node points to the second node.

A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.

Devices and techniques for thread-based processor halting are described herein. A processor monitors control-status register (CSR) values that correspond to a halt condition for a thread. The processor then compares the halt condition to a current state of the thread and halts in response to the current state of the thread meeting the halt condition.

A system comprising: a first subsystem comprising at least one first processor, and a second subsystem comprising one or more second processors. A first program is arranged to run on the at least one first processor, the first program being configured to send data from the first subsystem to the second subsystem. A second program is arranged to run on the one more second processors, the second program being configured to operate on the data content from the first subsystem. The first program is configured to set a checkpoint at one or more points in time. At each checkpoint it records in memory of the first subsystem i) a program state of the second program, comprising a state of one or more registers on each of the second processors at the time of the checkpoint, and ii) a copy of the data content sent to the second subsystem since the respective checkpoint.

The present disclosure provides a multi-core processor. The multi-core processor comprises a plurality of cores and a debug circuit, the debug circuit comprising debug circuits in the same number as that of the cores, transmission controllers in the same number as that of the cores, and a master control circuit, each of the debug circuits being connected to one core and one transmission controller, respectively, and all transmission controllers being connected to the master control circuit. Each of the debug circuits is configured to generate a debug event signal and respond to the generated debug event signal or received debug event signals generated by other debug circuits. Each of the transmission controllers is configured to respectively control transmission of the debug event signal between the respectively connected debug circuit and the master control circuit. The master control circuit is configured to forward debug event signals among different transmission controllers. The present disclosure can realize rapid configuration and control of debug event signal transmission, and at the same time lower power consumption of a debug circuit.

Mapping input locations to enable execution of second executable code using trace data gathered during execution of first executable code. A trace of a prior execution of the first code, and the second code, are accessed. The trace stores data of an input that was consumed by first executable instructions of the first code. It is determined that the stored data of the input is usable as an input to second executable instructions of the second code. A difference in how the first instructions accessed the input during recording, as compared to how the second instructions expect to access input, is identified. Based on the identified difference, a location transformation is determined that would enable the second instructions to access the stored data. Execution of the second instructions is emulated using the stored data, including projecting the location transformation to enable the second instructions to access the stored data.

Embodiments generate effective mutation directions for fuzzing by using an abstract interpretation engine that for each of a set of input variables determines whether, for an input value range, a source code comprises a potential bug. The abstract interpretation engine generates a list of potential bugs that is provided to a machine learning engine (e.g., a reinforcement learning engine) that, iteratively for each potential bug, generates a learned input value range that is narrower than the input value range. The learned input value range is provided to the abstract interpretation engine, which updates the input value range, and to a fuzzer, which limits a search space for generating a set of seeds that is used to identify bugs in the source code.

A launch of a user application is detected and a clone instance of that user application is initiated. A trigger is detected. The trigger is within the user application and is for a simulation of a user action. The user action is executed in the clone instance in response to detecting the trigger. The results of the user action are displayed to a user of the user application.

The present disclosure discloses a conflict detection method for Internet of Things (IoT) device scheduling, relating to the technical field of the IoT, and specific steps include: acquiring data of a device model; converting a device scheduling instruction into a conditional instruction according to the data of the device model; determining a scheduling conflict rule according to device scheduling conflicts in historical data; detecting whether the conditional instruction is in a conflict state based on the scheduling conflict rule; if the conditional instruction is in a conflict state, performing a first conflict resolution, or if the conditional instruction is in a non-conflict state or after a conflict is resolved, performing a second detection; converting, in the second detection, the conditional instruction into an SMT formula, inputting the SMT formula into an SMT solver for detection, and determining whether the conditional instruction is in a conflict state; and if the conditional instruction is in a conflict state, performing second conflict resolution, or if the conditional instruction is in a non-conflict state or after a conflict is resolved, executing the conditional instruction. The present disclosure ensures consistency between different services of the IoT, and a rule-based method and an SMT solver-based method are adopted to perform conflict detection.

A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.